Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2000-01-28
2001-07-03
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S284000, C327S149000, C327S158000, C327S161000, C365S233100, C375S376000
Reexamination Certificate
active
06255880
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated circuits (ICs). More particularly, the invention relates to a delay-lock loop (DLL) circuit and method for an IC.
BACKGROUND OF THE INVENTION
Clock signals are used in virtually every IC and electronic system to control timing. For example, every time there is a rising edge on a clock signal, all the flip-flops in a circuit may change state. Clearly, clocks are often heavily loaded signals, and may be bussed throughout a very large IC. Even with specially-designed global buffers, there is typically a delay between the clock edge received by the IC at the pad, and the clock edge received by the last-served flip-flop on the IC (i.e., between the “input clock signal” and the “destination clock signal”). This delay, designated herein as t
d
, may cause difficulties in interfacing between ICs, or simply slow down the overall system speed. Input data may be provided in synchronization with the input clock signal, while output data is typically provided in synchronization with the destination clock signal. Further, t
d
often varies not only between different ICs, but on a single IC with temperature and voltage as well. It is highly desirable to have a circuit and method for synchronizing a destination clock signal with an input clock signal, so that the destination clock signals of various ICs can be commonly synchronized by synchronizing each destination clock signal to a common input clock signal.
This clock synchronization procedure is often performed using a phase-lock loop (PLL) or delay-lock loop (DLL). However, known PLLs and DLLs consume a great deal of silicon area. Additionally, PLLs are often analog in nature and take an extremely long time to simulate, and a design that works in one manufacturing process may stop working when manufactured using another process. Further, analog PLLS can be particularly sensitive to radiation. Therefore, PLLS are very difficult to design, and often are not feasible in a given circuit or system. Known DLLS are also very complicated and difficult to design. Further, known DLLs require many input clock cycles to “lock”, i.e., to synchronize a destination clock signal to an input clock signal. As described below, known DLLs also typically run continuously during the entire time the two clock signals must be synchronized, frequently adjusting the destination clock signal to keep it properly synchronized. This constant adjustment not only requires a large and complicated state machine, it also injects a lot of noise into the clock network. Because a noisy clock signal can cause enormous problems in a sensitive IC circuit, a large stabilizing capacitor is often required between the positive power supply (VDD) and the zero voltage level (ground). For one or more of these reasons, clock synchronization is often not feasible using known circuits and methods.
Therefore, it is desirable to provide a delay-lock loop circuit and method using a fairly simple circuit that consumes a relatively small amount of silicon area and locks in a few clock cycles.
SUMMARY OF THE INVENTION
The invention provides a delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. Unlike previous circuits and methods, a single synchronization step is sufficient, provided that the frequency of the input clock signal is stable. A circuit according to the invention includes an input clock terminal supplying an input clock signal, and a delay line driven by the input clock signal and supplying a plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays. A clock multiplexer selects from among these intermediate clock signals, under control of a multiplexer control circuit, the clock signal that provides the necessary additional delay to synchronize the feedback clock signal to the input clock signal, i.e., the clock signal subject to a delay about equal to (e.g., closest to but not exceeding) the delay needed to bring a first (e.g., rising) edge of the feedback clock signal into synchronization with the same (e.g., rising) edge of the input clock signal. The output clock signal from the clock multiplexer is distributed through the clock network to provide the distributed clock signal as well as the feedback clock signal. (In another embodiment, the intermediate clock signal selected by the clock multiplexer is the intermediate clock signal subject to a delay closest to and exceeding the delay needed to synchronize the feedback and input clock signals.)
The multiplexer control circuit essentially counts the number of unit delays between a first (e.g., rising) edge of the feedback clock signal and the same (e.g., rising) edge of the input clock signal. This delay period is the additional delay that must be added to the feedback clock to bring the two clock, into synchronization. This number is then used to select the correct intermediate clock signal.
In one embodiment, the DLL circuit includes an option to disable the circuit. A disable control signal is applied to t multiplexer control circuit to select the input clock signal the output clock signal. Therefore, when the DLL circuit is disabled, no adjustment of the feedback clock signal is performed.
In yet another embodiment, a status generator circuit is provided that provides a status signal after a predetermined number of input clock cycles have elapsed. This status signal may be used by other circuits to disable the output clock signal until the output clock signal has settled into a reliably predictable pattern.
An advantage of the invention is that once the two clocks are synchronized, they need not be resynchronized unless the frequency of the input clock signal changes. Although the feedback clock signal may not be exactly synchronized to the input clock signal (the degree of accuracy depending on the granularity of the unit delay compared to the measured delay), the offset between the two clock signals does not change with time, and no subsequent adjustments need be made, as with prior art DLL circuits. Therefore, the circuit and method of the invention inject significantly less noise into the IC than known methods. Further, this “one-shot” capability (i.e., the ability to synchronize the two clocks in a single synchronization step) means that the circuit of the invention is much easier to simulate, and thus to design, than known DLL circuits.
Another advantage of the invention is that the circuit is smaller and therefore less expensive to implement than known DLL circuits, because no large state machine is required. Therefore, using the DLL circuit of the invention, clock synchronization capability can be added to smaller and less expensive ICs than was previously feasible.
In one embodiment, the “one-shot” concept of the invention is applied to a conventional DLL, thereby reducing the number of clock cycles required to synchronize the global and local clocks. However, as in conventional DLLS, the feedback clock is still monitored and adjusted at each clock cycle to maintain a continuous check and synchronization.
REFERENCES:
patent: 5245637 (1993-09-01), Gersbach et al.
patent: 5537069 (1996-07-01), Volk
patent: 5994938 (1999-11-01), Lesmeister
patent: 6040472 (2000-03-01), Martin
patent: 6100735 (2000-08-01), Lu
Xilinx Application Note, “Using the Virtex Delay-Locked Loop”, XAPP132, Oct. 21, 1998.
Callahan Timothy P.
Cartier Lois D.
Nguyen Minh
Xilinx , Inc.
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