One-shot circuit for use in a PLL clock recovery circuit

Details One-shot circuit for use in a PLL clock recovery circuit One-shot circuit for use in a PLL clock recovery circuit

1990-09-18

1992-06-23

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

307273, 307288, 331 8, 331 25, 331113R, H03K 3284, H03L 706

Patent

active

051246694

ABSTRACT:
A one-shot whose period is a fraction or multiple of the VCO period in a clock recovery circuit. In a clock recovery circuit using PLL, the one-shot is coupled to the PLL in order to enable/disable the phase detector for cases when the data stream does not consist of uniformly spaced pulses. Without a one-shot, the phase detector in the PLL generates a large error signal whenever a clock pulse occurs without a data pulse. During the times when the phase detector is enabled, a phase comparison is made between the next data edge and the next clock edge. When this comparison is completed, the phase detector is disabled again. In order for the PLL to average out the effects of noise and jitter, the phase detector is enabled one half clock period before the data edge. By doing this, the data edge can shift up to one half clock period. The one-shot of the present invention generates a delayed data signal whose rising edge is used to enable the phase detector, and whose falling edge is compared with the clock edge for disabling the phase detector.

REFERENCES:
patent: 3673559 (1972-06-01), Schwartz
patent: 3719835 (1973-03-01), Eberhard
patent: 3838344 (1974-09-01), Tanimoto
patent: 4017806 (1977-04-01), Rogers

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