Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
2006-04-18
2010-10-05
Payne, David C (Department: 2611)
Pulse or digital communications
Equalizers
Automatic
C375S229000, C375S233000
Reexamination Certificate
active
07809054
ABSTRACT:
Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
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Carballo Juan A.
Cranford, Jr. Hayden C.
Nicholls Gareth J.
Norman Vernon R.
Schmatz Martin L.
Bolourchi Nader
Dillon & Yudell LLP
International Business Machines - Corporation
Payne David C
LandOfFree
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