One's complement subtractive arithmetic unit utilizing two's com

Details One's complement subtractive arithmetic unit utilizing two's com One's complement subtractive arithmetic unit utilizing two's com

1977-01-28

1978-07-04

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

040992489

ABSTRACT:
The one's complement subtractive arithmetic unit comprises a parallel adder with a connection for providing an end-around carry, from the carry output of the most significant stage to the carry input of the least significant stage. The parallel adder is implemented utilizing multiple bit LSI ALU chips or microprocessor slices that provide group propagate and generate indication signals. Carry look-ahead chips responsive to the group propagate and generate indication signals provide a fast carry arrangement for the arithmetic unit. Circuitry is included to detect when all of the carry propagate indicators are on for providing a signal to the carry input of the parallel adder resulting in the equivalent performance of a one's complement subtractive arithmetic unit.

REFERENCES:
patent: 3700875 (1972-10-01), Saenger et al.
patent: 3805045 (1974-04-01), Larsen
patent: 3863061 (1975-01-01), Kazantzis et al.
patent: 3970833 (1976-07-01), Gehweiler et al.

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