One's complement adder

Boots – shoes – and leggings

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G06F 750

Patent

active

042989523

ABSTRACT:
A one's complement adder for adding two binary numbers A.sub.i, B.sub.i in the one's complement system is constructed from a conventional adder circuit by connecting the generate output signal G produced by the adder to the carry-in terminal of the adder. The value of the generate signal is independent of the signal applied to the carry-in terminal which prevents the adder from exhibiting sequential or indeterminate behavior.

REFERENCES:
patent: 3863061 (1975-01-01), Kazantzis et al.
patent: 3970833 (1976-07-01), Gehweiler et al.
patent: 4084252 (1978-04-01), Miller
S. Morguesan, "Complement Adders Give Unambiguous Zero Output", Electronic Engineering, vol. 48, No. 586, p. 25, Dec. 1976.

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