One nanosecond resolution programmable waveform generator

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

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Details

331 57, 331 74, 327116, 327141, 327175, H03K 301, H03L 706

Patent

active

053941144

ABSTRACT:
Generation of clock waveforms which have a frequency, phase offset, and duty cycle that is relative to a periodic reference signal. The outputs of a voltage controlled ring oscillator are directly applied to drive the inputs of a programmable AND, fixed OR array (PAL) to produce pulses of varied and phase offset and duty cycle. The phase offset has a resolution of one nanosecond. Additionally, the pulses generated can be ORed together within the PAL to produce clock waveforms that are multiples of the input frequency.

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National Semiconductor Preliminary Data Sheet titled CGS500 Programmable Timing Manager, Sep. 1991, 14 unnumbered pages. A Jul. 1991 and the Sep. 1991 Preliminary Data Sheets were distributed outside of National only with non-disclosure agreements.
Gazelle Microcircuits, Inc. Data Sheet titled GA1110 Multi-Phase Clock Generator Low-Skew TTl Clock Buffer, pp. 1-2 (no date, no author).
Gazelle Microcircuits, Inc. Data Sheet titled GA1210 Los-Skew TTL Clock Doubler Two-Phase Clock Generator, pp. 1-2 (no date, no author).
Ron Wilson, Creative Use of PLLs Solves Clock Skew Problem, Sep. 1, 1990, Computer Design, pp. 40-42.
Deog-Kyoon Jeong et al., Design of PLL-Based Clock Generation Circuits, Apr. 1987, Journal of Solid State Circuits, vol. 22, pp. 255-261.

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