Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2002-06-26
2004-06-15
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S595000, C438S957000
Reexamination Certificate
active
06750114
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a metal-insulator-metal (MIM) capacitor having a first spacer protecting an upper electrode and a second spacer protecting a lower electrode, and a method of manufacturing the same.
2. Description of the Related Art
Back of the line capacitors fabricated as part of the wire and via process are a required part of integrated circuit manufacturing. MIM capacitors have been in high volume manufacturing for several years and, for the foundry technologies, will see increasing use in the future. One basic problem with MIM capacitors is that if the sidewalls are vertical, then there is a potential for a leakage path down the capacitor sidewalls, which results in defective capacitors.
FIG. 1
provides an example of a MIM capacitor prone to leakage down the capacitor sidewalls and shows a convential capacitor structure including an upper electrode
102
, a dielectric layer
103
, and a lower electrode
104
, a via
107
, a via
140
, metal layer
170
, a via
172
, a via
174
, metal layer
176
, intermetal dielectric
106
and metal layer
160
.
To address this problem, conventional MIM capacitors have been fabricated by first etching an upper electrode using a first mask, and then etching the lower electrode using a second mask. A MIM capacitor created by this method of manufacture is depicted in
FIGS. 2 and 3
.
FIG. 2
is a conventional MIM capacitor that avoids a leakage problem and involves three additional mask layers. This structure includes a capacitor stack including an upper electrode
102
, a dielectric
103
, and a lower electrode
104
. Further, vias
107
,
140
,
172
, and
174
are also provided.
FIG. 3
is a conventional MIM capacitor that avoids a leakage problem and involves two additional mask layers.
FIGS. 2 and 3
show similar MIM capacitors, with a primary distinction that bottom plate of the MIM Capacitor depicted in
FIG. 2
is contacted from below and therefore requires three additional masks while the MIM Capacitor depicted in
FIG. 3
is contacted from above and involves only two additional masks. It is noted that
FIG. 3
additionally depicts an insulating diffusion barrier layer
105
configured to prevent diffusion of the metal layer
106
.
FIGS.
4
(A) and
4
(B) depict MIM capacitors in accordance with the present invention. FIGS.
5
(A),
5
(B),
5
(C),
5
(D), and
5
(E) depicts a method of manufacturing a MIM capacitor in accordance with the present invention. Although this configuration addresses the problem of leakage down the capacitor sidewalls, the additional mask layer leads to an increased cost and complexity associated with the fabrication process.
SUMMARY OF THE INVENTION
In view of the above and other problems of the invention and systems and technologies, it is an object of the invention to provide a MIM capacitor that is not prone to leakage down the capacitor sidewall and a method for manufacturing the MIM capacitor that is inexpensive and efficient (e.g., by reducing the number of mask steps required for fabrication of the capacitor structure).
According to one embodiment of the invention, this object is achieved by a capacitor structure formed on an insulation layer including a lower electrode formed on a surface of the insulation layer, a dielectric layer formed on a surface of the lower electrode, an upper electrode formed on a surface of the dielectric layer, a first spacer formed on a side portion of the upper electrode, and a second spacer formed on a side portion of the first spacer and a side portion of the lower electrode.
This capacitor structure may be formed by depositing a metal-insulator-metal capacitor stack on top of a via, masking and etching an upper electrode of the metal-insulator-metal capacitor stack, depositing and etching a first spacer on an edge surface of the upper electrode, defining a lower electrode of the metal-insulator-metal capacitor based on the first spacer, depositing and etching a second spacer on a surface of the first spacer and an edge of the lower electrode, and forming a wiring layer on a surface of the upper electrode and a surface of the second spacer. This capacitor structure and its corresponding method of manufacture provide a protected capacitor structure that is fabricated with increased efficiency (e.g., fewer mask steps).
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Adler Eric
Stamper Anthony Kendall
Chaudhari Chandra
McGinn & Gibb PLLC
Sabo, Esq. William D.
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