One-mask customizable phase-locked loop

Details One-mask customizable phase-locked loop One-mask customizable phase-locked loop

1998-08-31

2004-08-03

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S537000, C257S538000, C257S539000, C257S529000

Reexamination Certificate

active

06770949

ABSTRACT:

FIELD OF INVENTION
The invention relates generally to phase-locked loops (“PLLs”) and particularly, the invention relates to tuning and customizing PLLs.
BACKGROUND OF THE INVENTION
Phase-locked loops (PLLs) are generally systems that use feedback to maintain an output signal in a specific phase relationship with a reference, or input, signal. PLLs are useful for jitter reduction, skew suppression, frequency synthesis, and clock recovery in numerous systems such as communication, wireless systems, digital circuits, and disk-drive electronics. While PLLs have been known for over half a century, they have gained considerable popularity in the past two decades due to demands for higher performance and low cost electronic systems as well as advances in integrated-circuit process technologies.
Despite advances in integrated-circuit (IC) formation processes, variations in processes regularly occur among different fabrication facilities (“fabs”). For instance, the doping technique used at one fab may result in a different sheet resistance from that achieved with a different doping technique used at a second fab. Likewise, lithographic and etch techniques may result in variation of the dimensions of elements being formed.
Unfortunately, PLLs tend to be sensitive to the quality and type of components that they are composed of, and particularly to sheet resistance and feature dimensions. Thus, when a PLL is included in an IC, slight variations among the processes used by different fabs can cause significant variations in the performance of PLLs produced at the respective fabs. So, if one IC design that includes a PLL is sent to a first fab for fabrication, and the same design is sent to a second fab, the performance of the PLLs in each respective IC would be different.
Hence, when a sensitive circuit design such as a PLL is to be sent to multiple fabs, the circuit will be required to be redesigned for each fab to account for the nuances of each fab process. Such redesign requires adjustment of transistor values, resistor values, and/or capacitor values as well as the redesign and layout of various layers of which the IC is formed. When more than one fab is going to be used for a particular design, or the fab that is going to be used is unknown at the time of the design, this redesign process can be burdensome. Moreover, if any changes wish to be made to the PLL after it has been designed, for instance if the IC is going to be used in an application that requires a different center frequency than that designed, similar burdens will be confronted. Often too, PLLs are predesigned and/or prefabricated into gate arrays or other partially customizable ASICs. The ability of the users of these ASICs to tune or customize the PLL is typically unavailable.
SUMMARY OF THE INVENTION
A system and method in accordance with the invention minimizes the redesign burden in tuning and/or customizing PLLs on ICs. In one embodiment, variable resistors are placed in the PLL in places that facilitate tuning. The variable resistors are formed with a set of at least three contacts, where each contact is in electrical communication with a resistive area. A metal layer is used to form leads to the resistive area, where each lead is formed to be in electrical communication with only a selected subset of the contacts from the set. In one embodiment, only the uppermost metal layer used in forming the IC is used to form the leads. Because the uppermost metal layer is utilized, the resistor value can be adjusted simply by selecting the subsets of contacts that are to be in electrical communication with the uppermost metal layer. In this manner, only one metal layer needs to be adjusted in tuning and/or customizing a PLL, rather than having to redesign and re-layout all metal layers and vias in the IC.
Such a system and method allows greater portability of IC designs among fabs and also facilitates easy circuit customization.


REFERENCES:
patent: 3593069 (1971-07-01), Madden
patent: 4191964 (1980-03-01), Kant
patent: 4467312 (1984-08-01), Komatsu
patent: 4560583 (1985-12-01), Moksvold
patent: 4713680 (1987-12-01), Davis et al.
patent: 4845462 (1989-07-01), van de Grift et al.
patent: 5110758 (1992-05-01), Baskett
patent: 5493148 (1996-02-01), Ohata et al.
patent: 5621240 (1997-04-01), Ellis
patent: 2-199866 (1990-08-01), None
“Monolithic Phase-Locked Loops and Clock Recovery Circuits”, by Behzad Razavi, IEEE Press, 1996.
“CMOS Circuit Design, Layout, and Simulation”, pp. 480, 384-387, 393-394, R. Jacob Baker, Harry W. Li and David E. Boyce, IEEE Press, 1998.

Affiliated with

Also associated with

Rating

One-mask customizable phase-locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with One-mask customizable phase-locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and One-mask customizable phase-locked loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3352571