One hundred percent duty cycle sample-and-hold circuit

Details One hundred percent duty cycle sample-and-hold circuit One hundred percent duty cycle sample-and-hold circuit

1986-10-03

1987-09-01

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307491, 328151, G11C 2702

Patent

active

046911251

ABSTRACT:
A switched capacitor sample-and-hold circuit which compensates offset voltage error and switch feedthru error while having a one hundred percent duty cycle is provided. Two amplifiers are utilized. A first operational amplifier is disconnected from a second operational amplifier while being autozeroed. An input voltage is sampled onto an input capacitor. The input capacitor is disconnected from the input voltage and then coupled to the second operational amplifier which is in a unity gain configuration. After the sampled input voltage is charged onto an output load, the first operational amplifier is disconnected from the second operational amplifier and the sampling process is repeated. The second operational amplifier is also offset voltage compensated by the first operational amplifier.

REFERENCES:
patent: 4404479 (1983-09-01), Toyomaki
patent: 4439693 (1984-03-01), Lucas et al.
patent: 4542304 (1985-09-01), Swanson
patent: 4546324 (1985-10-01), Bingham et al.
patent: 4570080 (1986-02-01), Swanson
patent: 4585956 (1986-04-01), Lie
patent: 4587443 (1986-05-01), Van de Plassche

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