One gate delay output noise insensitive latch

Details One gate delay output noise insensitive latch One gate delay output noise insensitive latch

2007-01-16

2007-01-16

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S208000, C327S218000

Reexamination Certificate

active

10874041

ABSTRACT:
A one gate delay output noise insensitive latch includes an input node, an output node, a storage node, a not storage node, and a data clock line. A primary latch element is connected to the input node, the output node, and the data clock line. A mirror primary latch element is connected to the input node in parallel with the primary latch element, to the storage node, and to the data clock line. A weak keeper is connected to the storage node and to the not storage node. A strong enabled tri-state keeper is connected to the not storage node, to the data clock line, and to the output node. The input node is either a dynamic data input node or a static data input node. Optionally, the weak keeper is also clock enabled.

REFERENCES:
patent: 4495629 (1985-01-01), Zasio et al.
patent: 5311070 (1994-05-01), Dooley
patent: 6097230 (2000-08-01), Bareither
patent: 6348824 (2002-02-01), Grondalski et al.
patent: 6433601 (2002-08-01), Ganesan
patent: 6690205 (2004-02-01), Alvandpour
patent: 2004/0080351 (2004-04-01), Hirata et al.
patent: 2005/0110522 (2005-05-01), Hoekstra

Affiliated with

Also associated with

Rating

One gate delay output noise insensitive latch does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with One gate delay output noise insensitive latch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and One gate delay output noise insensitive latch will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3756085