Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-11-28
2004-01-27
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06684235
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to wavelet systems, and more particularly to one-dimensional wavelet transform systems.
BACKGROUND
An example programmable logic device (PLD) is the field programmable gate array (FPGA), first introduced by Xilinx, Inc., in 1985. PLDs such as FPGAs are becoming increasingly popular for use in electronics systems. For example, communications systems employ FPGAs in large measure for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability.
Advances in semiconductor process technology are delivering FPGAs having logic densities in the range of a million system gates and having operating speeds in excess of 100 MHz. These powerful devices are capable of and have been used to implement digital signal processing (DSP) algorithms which are inherently parallel and normally require multiple DSP microprocessors in order to meet the high data rates. It is feasible to implement such algorithms on a single FPGA because such devices offer a programmable architecture.
The discrete wavelet transform (DWT) is a useful and efficient signal and image decomposition method with many interesting properties. This transformation, which is similar to the Fourier transform, provides information about the frequency content of signals. However, unlike the Fourier transform, DWT is more natural and fruitful when applied to non-stationary signals, such as speech and images.
The flexibility offered by DWT allows researchers to develop suitable wavelet filters for particular applications. For example, in the compression of fingerprints a particular set of biorthogonal filters, Daubechies biorthogonal spline wavelet filters, has been found to be effective. This flexibility is nonexistent in the discrete-cosine transform for image compression.
The latest standards for image and video compression, JPEG and MPEG, include wavelet transforms as the means for image and video signal decomposition. In addition to efficient image decomposition for compression and coding, wavelet transform is applied to images for filtering and enhancement. The filtering algorithms, generally referred to as denoising, have shown robust and effective performance in the removal of noise from images with minimal side effects (blurring).
In many image processing applications, including compression, denoising, and enhancement, real-time processing of a two-dimensional wavelet transform is required. Flexibility in customizing the wavelet transform with regard to the filters and the structure of the wavelet decomposition tree are also desirable. Most ASIC implementations are developed for specific wavelet filters and/or wavelet decomposition trees, which renders ASIC solutions useless for applications that require different filters and/or different decomposition trees. A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.
SUMMARY OF THE INVENTION
In various embodiments, a computation engine is provided for one-dimensional wavelet systems. The computation unit is adaptable to implement discrete wavelet transform, discrete wavelet packet, and custom wavelet trees.
The computation engine includes a plurality of register banks having input ports arranged to receive input sample values and a multiplexer coupled to the output ports of the register banks. A processing unit is configured to perform the forward or inverse wavelet transform for data values that are sequenced through the register banks and multiplexer by a control unit. Depending on the structure of the wavelet tree, the computation engine can implement multiple stages of the wavelet transform and/or multiple filter elements of the transform. All or part of the computation engine can be implemented on a programmable logic device, for example, a field programmable gate array, to provide further design flexibility.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims, which follow.
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Reza Ali M.
Turney Robert D.
Cartier Lois D.
Malzahn David H.
Maunu LeRoy D.
Xilinx , Inc.
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