One dimensional systolic array architecture for neural network

Details One dimensional systolic array architecture for neural network One dimensional systolic array architecture for neural network

1995-05-15

1998-08-25

MacDonald, Allen R.

395 27, G06F 1518

Patent

active

057991340

ABSTRACT:
A circuit for implementing a neural network comprises a one dimensional systolic array of processing elements controlled by a microprocessor. The one dimensional systolic array can implement weighted sum and radial based type networks including neurons with a variety of different activation functions. Pipelined processing and partitioning is used to optimize data flows in the systolic array. Accordingly, the inventive circuit can implement a variety of neural networks in a very efficient manner.

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