One-dimensional interpolation circuit and method based on modifi

Details One-dimensional interpolation circuit and method based on modifi One-dimensional interpolation circuit and method based on modifi

1991-02-07

1992-09-15

Nguyen, Long T.

Boots, shoes, and leggings

G06F 738

Patent

active

051483815

ABSTRACT:
An interpolator array having a plurality of interpolator array cells is provided for receiving first and second input values to be interpolated and an interpolator weight term, to provide an interpolated output. A bit of each of the two input values to be interpolated is received by an interpolator array cell and applied to a selecting circuit within a cell of the interpolator array. Additionally, an interpolation weight bit of the interpolation weight term is applied to the selection circuit. The selecting circuit applies either the input bit of the first input value or the input bit of the second input value to an adder within the interpolator cell in accordance with the value of the interpolation weight bit. An interpolator array cell also receives a partial product input and a carry-in input and applies these additional inputs to the adder. The adder provides a partial product output and a carry-out in accordance with the applied inputs.

REFERENCES:
patent: 4493048 (1985-01-01), Kung et al.
patent: 4727503 (1988-02-01), McWhirter
patent: 5020014 (1991-05-01), Miller et al.
"Principles of CMOS VLSI Design", Weste and Eshraghica, Addison-Wesley, 1985, pp. 344, 345.
"Computer Arithmetic--Principles, Architecture, and Design", Kai Hwang, John Wiley and Sons, 1979, pp. 161-165.

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