One clock address pipelining in segmentation unit

Details One clock address pipelining in segmentation unit One clock address pipelining in segmentation unit

1989-08-04

1993-04-20

Dixon, Joseph L.

Boots, shoes, and leggings

3642318, 364254, 3642543, 3642551, 3642555, 364258, 3642581, 364DIG1, G06F 934, G06F 1200, G06F 1208

Patent

active

052049531

ABSTRACT:
A microprocessor which comprises a three input adder, a two input adder, apparatus for providing the components of a virtual address to the first and second adders on a first clock period, and apparatus for providing a segment base address to the first adder on the first clock period, apparatus for determining the type of addresses generated by the adders on a second clock period and for generating an output address on the second clock period, and apparatus for determining access violations during a third clock period.

REFERENCES:
patent: 4783757 (1988-11-01), Krauskopf
Intel Microprocessing Peripheral Handbook, vol. 1, 1988, pp. 4-12.fwdarw.4-14, 4-68.fwdarw.4-78.

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