Boots – shoes – and leggings
Patent
1993-10-26
1995-04-18
Harvey, Jack B.
Boots, shoes, and leggings
3642318, 364238, 364240, 3642402, 364247, 3642474, 3642478, 364254, 3642543, 3642551, 3642563, 364258, 3642581, 364259, 3642599, 364DIG1, G06F 934, G06F 1200, G06F 1208
Patent
active
054086264
ABSTRACT:
A microprocessor which comprises a three input adder, a two input adder, apparatus for providing the components of a virtual address to the first and second adders on a first clock period, and apparatus for providing a segment base address to the first adder on the first clock period, apparatus for determining the type of addresses generated by the adders on a second clock period and for generating an output address on the second clock period, and apparatus for determining access violations during a third clock period.
REFERENCES:
patent: 4594655 (1986-06-01), Hao et al.
patent: 4783757 (1988-11-01), Krauskopf
Intel Microprocessor and Peripheral Handbook, vol. 1, 1988, pp. 4-12.fwdarw.4-14, 4-68-4-78.
Harvey Jack B.
Intel Corporation
Whitfield Michael A.
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