One-chip microprocessor with error detection on the chip

Details One-chip microprocessor with error detection on the chip One-chip microprocessor with error detection on the chip

1994-02-15

1999-11-16

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

712 32, 714 48, 714800, 714801, 714805, G06F 1100

Patent

active

059875852

ABSTRACT:
A one-chip microprocessor, in which a built-in cache memory unit 20 has parities, and a cache parity generating & checking unit 21 checks parity of data read from the built-in cache memory unit 20, and when parity error is detected, outputs an internal cache parity error signal 50 to an instruction execution unit 23. By this, the instruction execution unit 23 suspends instruction execution and outputs a processor error signal 37. Accordingly, by checking parity errors of data of built-in memory and inputted address/data, instruction execution are immediately suspended to limit malfunction at least, thereby improving reliability. And by storing kinds of bus operation and errors in a register at the time of error generation, restoring possibility of system level is improved.

REFERENCES:
patent: 4195206 (1980-03-01), Baichtal
patent: 4858234 (1989-08-01), Hartwell et al.
patent: 5214745 (1993-05-01), Sutherland
patent: 5313627 (1994-05-01), Amini et al.
patent: 5402429 (1995-03-01), Stessens
"A 64b CMOS Mainframe Execution Unit Macrocell with Error Detection Circuit", by Takehisa Hayashi et al, IEEE 1991 Custom Integrted Circuits Conference, pp. 15.6.1-15.6.4.

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