Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1998-11-25
2001-10-02
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S032000, C712S036000, C712S041000, C710S120000
Reexamination Certificate
active
06298432
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to information processing systems, and in particular, to a one-chip microcomputer which employs RISC technology to execute interrupt processing and numeric operations at high speed.
2. Description of the Prior Art
Conventional RISCs (Reduced Instruction Set Computers) have been developed as engines for computers mainly to increase the speed of arithmetic operations. The instruction length of the RISCs is normally 32 bits, fixed.
In a one-chip microcomputer employing RISC, since the code efficiency is low, interrupt processing is performed by another chip. Thus, the speed of the interrupt processing is low. In addition, with a conventional one-chip microcomputer, arithmetic operations cannot be performed at high speed.
OBJECTS AND SUMMARY OF THE INVENTION
The present invention is made in view of the above problems. The invention employs RISC technology in a one-chip microcomputer so as to allow both interrupt processing and arithmetic operations to be performed at high speed.
In one illustrative embodiment of the invention, a one-chip microcomputer includes a RISC type processor and one or more coprocessors which are coupled to the RISC processor via a coprocessor bus. The coprocessors include one or more registers which may function as control registers for the RISC type processor.
In another illustrative embodiment of the invention, a one-chip microcomputer includes a RISC type processor, one or more coprocessors, one or more code buffers and one or more data buffers. The coprocessors, code buffers and data buffers are respectively coupled to the RISC processor via a coprocessor bus, instruction bus and data bus. The three buses are distinct, and therefore information may be transferred over each of the buses independently.
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An Meng-Al T.
El-Hady Nabil
Frommer William S.
Frommer & Lawrence & Haug LLP
Polito Bruno
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