One-bit-out-of-N-bit checking circuit

Details One-bit-out-of-N-bit checking circuit One-bit-out-of-N-bit checking circuit

1976-12-08

1978-05-02

Atkinson, Charles E.

Communications: electrical

Digital comparator systems

G06F 1108

Patent

active

040877868

ABSTRACT:
A one-bit-out-of-n bit checking circuit is comprised of k serially connected detector levels. A first one of the detector levels accommodates n input signal lines and successively higher ones of the detector levels have one half the number of input signal lines as does the next lower detector level. Each detector level is comprised of a plurality of logic blocks with each logic block being connected to a separate pair of input signal lines. Each logic block in each level detects the presence of excitation signals on both input signal lines of the pair of input signal lines and generates an error signal in response thereto. Each logic block also detects the presence of an excitation signal on one input signal line of the pair of input signal lines and in response thereto propagates the excitation signal through successively higher detector levels to the k.sup.th detector level. The k.sup.th detector level generates an excitation signal output in response to the presence of an excitation signal on one and only one of the input signal lines applied to the k.sup.th level.

REFERENCES:
patent: 3458240 (1969-07-01), Hanson
patent: 3559167 (1971-01-01), Carter et al.
patent: 3614735 (1971-10-01), Mauger et al.
patent: 3619583 (1971-11-01), Arnold
patent: 3744024 (1973-07-01), Russell et al.
patent: 3855536 (1974-12-01), Neuner
patent: 3886520 (1975-05-01), Christensen
Williams, Parity-Check Generate Circuit, IBM Technical Disclosure Bulletin, vol. 12, No. 4, Sep. 1969, p. 623.
Greenhalgh, Exclusive "OR" Circuit, IBM Technical Disclosure Bulletin, vol. 2, No. 6, Apr. 1960, pp. 98-99.

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