One-bit full adder

Registers – Transfer mechanism – Traveling pawl

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G06F 750

Patent

active

039783294

ABSTRACT:
A high-speed, low-power 1-bit adder includes a combination of current-mode switches connected in a dual tree configuration in series with respective constant current sources and summing resistors. Input operand signals select particular tree paths, thereby controlling the voltage appearing across the summing resistors and sum and carry output drivers responsive to these voltages.

REFERENCES:
patent: 3519810 (1970-07-01), Priel et al.
MECL Integrated Circuits Data Book, Motorola, Inc., 1973, pp. 5-42 to 5-44.

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