One bit error correction method having actual data reproduction

Details One bit error correction method having actual data reproduction One bit error correction method having actual data reproduction

1993-02-11

1995-04-18

Gordon, Paul

Excavating

371 377, G06F 1110

Patent

active

054084768

ABSTRACT:
A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st.about.n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.

REFERENCES:
patent: 4468770 (1984-08-01), Metcalf et al.
patent: 4928280 (1990-05-01), Nielson et al.
patent: 5062111 (1991-10-01), Gotou et al.

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