Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
1997-01-30
2001-01-30
Hjerpe, Richard A. (Department: 2774)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S182000, C345S182000, C345S205000, C345S205000, C345S519000, C345S504000
Reexamination Certificate
active
06181353
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention relates in general to on-screen display (OSD) and in particular to a device that performs complex, overlaying of characters, graphics, etc. utilizing a small-scale display scan memory.
2. Prior Art
Conventional OSD devices have generally been designed to first store in display memory simple object characters, their colors and other very basic attributes. These OSD devices then read the display data from the display memory, according to incoming horizontal and vertical synchronizing pulses, retrieve corresponding font data from a character generator ROM and finally display the characters with the specified colors and other attributes. These steps require specialized hardware OSD circuitry.
A more recent architecture is based on a bit map display system, where complex OSD is made possible by allocating each pixel multiple bits in a large-scale, external, video display memory, that is controlled by a dedicated, graphics controller integrated circuit.
The extensive use of hardware circuitry in the conventional OSD devices has not only inherently limited their complex OSD capabilities, but have made them much less flexible, requiring extensive redesigning every time improvements are called for. The bit map display system, while allowing complex OSD, make their host products costly because they require a large-scale, external memory and a dedicated integrated circuit for fast display data generation.
SUMMARY OF THE INVENTION
The present invention uses a hybrid OSD device architecture to meet complex on-screen display needs more flexibly than the conventional, dedicated OSD hardware. The present invention uses high speed, dynamic pixel generation circuitry, built around a microprocessor and software to eliminate the need for large-scale display memory. This reduction in memory results in a substantially lower cost than bit map display system.
To achieve complex OSD, the invention uses a two scan line display memory as a pixel memory. The memory devices each hold data representing one horizontal scan line. This small-scale memory is combined with the following components:
a) A RAM memory space holding compressed, hierarchically-structured and multiple-type display data;
b) A ROM memory space holding character fonts, graphics icon data and dynamic pixel generation software;
c) A dedicated, high speed, dynamic pixel generation circuit;
d) color palette registers;
e) on-screen display circuits; and
f) either a microprocessor or a sequence circuit with equivalent computational capabilities.
The major components of the invention will be briefly described. The display pixel memory holds pixel data for two horizontal scan lines. A data block represents sixteen (16) pixels, each pixel being allocated four (4) bits. A sixteen pixel array (64 bits) is manipulated in a single cycle. If the horizontal resolution is 640 pixels, the total capacity of the display pixel memory is 2×4×640 bits (2 lines, 4 bits per pixel, 640 pixels per line).
The compressed, multiple-typed, display data in the RAM memory space includes:
a) character display data including attributes and character data;
b) icon display data (icon number);
c) button display data (display frame type and coordinates) for buttons that may be selected by a user through a graphical user interface;
d) cursor display data (cursor type and coordinates);
e) half-tone display data (coordinates for partial-brightness display).
The ROM memory device keeps the following data:
a) character font pattern;
b) graphics icon data (definitions of all pixels in the individual icon, using 4 bits for each pixel);
c) dynamic pixel generation control software.
In the example provided below, fonts are sixteen (16) pixels wide and either eight (8), sixteen (16), or thirty-two (32) pixels tall. If the font is ten (10) or twenty (20) pixels tall, the excess data exceeding the integral power of two (e.g. 8 or 16) is separately defined, to minimize the pixel data block. For example, ten words of pixel data are separated into eight words and two words of data because the character font can be placed in any location of the memory, so eight words of data are placed in one memory area and the remaining two words are placed in another area. The graphics icons use four 16 bit-words for a single scan line and may be eight, sixteen or thirty-two pixels tall, similar to the character font. As described with respect to the character font, excess bits may be stored in a separate area.
The dedicated, high speed, dynamic display generation circuit consists of two modules. One module is the font address/attribute data separation circuit, which separates the character data from the attribute data. The font address/attribute data separation circuit also calculates the character font address from the separated character data and an offset address stored in an offset address register to determine the address of the character font in the ROM memory. The other module is a dynamic pixel generation circuit which generates pixel data in a single clock cycle based on the separated attribute data and the character data read from the ROM memory.
The font address/attribute data separation circuit includes:
a) a scan line register to point to the current relative scan line position within a font;
b) an AND circuit and a shifter circuit for extracting character data;
c) an offset address register for holding the starting memory address of the character data;
d) a compressed display data register for loading the compressed character display data;
e) two attribute registers for holding color and some attributes; and
f) a font address register.
The dynamic pixel generation circuit includes:
a) a pair of character font registers;
b) a right/left fringe and immediate value generation circuit;
c) a right barrel shifter and smoothing circuits;
d) a pair of mixer registers;
e) a pair of 4×16-bit pixel registers;
f) a pixel mode register for specifying a pixel generation mode; and
g) a pixel generation command decoder circuit.
There are fourteen color palette registers, each of which holds six bits; two each for the red, the green and the blue component of RGB. Each pixel is represented by a four bit color data. If the four-bit pixel data is all zeros (0000), a transparent pixel is “displayed”, resulting effectively in no overwriting of the background for that pixel position. If set to (0001), the pixel color is black. The remaining 14 four bit combinations (0010-1111) are used to access one of the color palette registers. The display circuits include a dot clock counter, circuits to control the display start position and the maximum display width, and timing signal generation circuits for the OSD display. A microprocessor or a sequence circuit implements the display software and transfers the sixteen bits of data to each module.
Two horizontal scans of display pixel memory have a particular role respectively in a single horizontal period. One of the pixel memories is used to display the complex pixel pattern on the display device and the other pixel memory holds newly generated display data. The process is repeatedly implemented at the input of the horizontal sync signal and is continued through the vertical region. By using this technique, and without having a large scale display memory, the complex OSD display process is carried out in real time by following the horizontal sync signal.
The RAM in the microprocessor maintains multi-layer structured display data which are compressed in several different formats. The compressed data is expanded in order and the expanded pixel data is stored into pixel memory. The newly generated pixel data is held in a first pixel register group and another pixel register group holds the previously generated pixel data read from the pixel memory. The contents of the two pixel register groups are overlaid and the result is stored into pixel memory. Thus, the complex OSD is processed by overlaying newly expanded display data layer by layer.
The compressed display data, including character data and the at
Cantor & Colburn LLP
Dinh Duc
Hjerpe Richard A.
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