Coded data generation or conversion – Converter compensation
Reexamination Certificate
2000-05-25
2002-07-16
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S120000
Reexamination Certificate
active
06420983
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to analog-to digital converters (“ADCs”), and more particularly relates to methods and apparatus for improving the performance of flash ADCs.
BACKGROUND OF THE INVENTION
Analog-to-Digital converters (ADC) are an important class of semiconductor components used widely in signal processing, instrumentation, communications and data storage. FIGS.
1
(A) and
1
(B) show a portion of a flash ADC
10
, in two different modes. FIG.
1
(A) shows the flash ADC
10
in auto-zero mode, while FIG.
1
(B) shows the flash ADC
10
in sample conversion mode. A resistor ladder
12
is connected between plus and minus reference voltages V
REF
+ and V
REF
−, respectively, to form 2
n
evenly spaced analog reference voltages, of which two are shown in FIG.
1
(A). A charge corresponding to these 2
n
reference voltages is stored on each of 2
n
corresponding capacitors
18
. The ADC
10
shown in FIGS.
1
(A) and (B) has a resolution of n+1 bits.
An analog input voltage V
IN
is captured periodically by a sample and hold (“SH”) circuit
14
, and, as shown in FIG.
1
(B), is compared to the 2
n
reference voltages in a corresponding number of comparators arrayed along these reference voltages. The comparator function is provided in the ADC
10
of FIG.
1
(B) by the combining of V
IN
and the reference voltages from the charge stored on the array of capacitors
18
. When V
IN
overcomes the reference voltage on a particular capacitor in the array
18
, the resulting positive voltage is amplified by the preamps P
1
and P
2
, tripping an associated latch
16
, and thus storing a data value of “
1
.” Assigning a number to each such comparator, the number of the comparator in the array at which the analog input goes from being below to being above the reference voltage corresponds to the digital representation of the analog input.
As the speed of flash ADCs has grown, various problems have arisen which need to be solved. One problem is the error in flash ADCs from the mismatch in the comparators. This mismatch changes the analog value at which the output of a comparator changes from zero to one, thus degrading the accuracy of the ADC. A solution developed to correct this problem is to auto-zero the comparators in order to cancel the offset. Usually, this offset correction is stored as a voltage on a storage capacitor.
Since capacitors slowly leak charge, it is necessary to perform this auto-zero operation on the array of comparators periodically. In low speed flash ADCs, which have long clock cycles, this auto-zero function can be done on every clock cycle. However, the clock cycle of a high speed ADC is too short for the auto-zero function to finish. Therefore, in high speed ADCs the auto-zero function must be performed during idle periods.
However, for some applications, such as communications applications, the idle times are not available. A common technique used to overcome this problem is to auto-zero only one comparator at a time. An extra comparator is used temporarily, to take over the functionality of the comparator being auto-zeroed. See, for example, S. Tsukamoto et al., “A CMOS 6-b, 200 MSample/s, 3V Supply A/D Converter for a PRML Read Channel LSI,” IEEE
J. Solid-State Circuits
, Vol. 31, No. 11, pp. 1831-1836. This technique is referred to herein as on-line auto-zero, since it allows the ADC to convert continuously without being taken off-line to perform its auto-zero function.
Another problem encountered in flash ADCs is the speed bottleneck in the SH circuit at the front end. One technique used to reduce this bottleneck is to reduce the capacitive load on the SH circuit, thereby reducing the time needed to provide a reliable sample voltage. This is accomplished by eliminating the first stage preamps of half of the comparators, so that the SH load is reduced by a factor of two. The outputs of two adjacent first stage preamps are interpolated to provide inputs for the second stage preamps of the comparators that do not have first stage preamps.
This technique is used in the ADC shown in FIGS.
1
(A) and (B), in which half of the first stage preamps have been eliminated. Note that the analog signal path in these figures may be differential even though it is shown as single-ended in the figure for clarity. Note also that some of the P
2
preamps are interpolating preamps, and are identified by P
2
′. These P
2
′ preamps interpolate between adjacent P
1
preamp outputs.
As mentioned above, FIG.
1
(A) shows the ADC
10
configuration during an auto-zero (“AZ”) period. There are actually two phases of this auto-zero period. Since a second stage interpolating preamp P
2
′ requires a zero input to perform its auto-zero, during the first phase of AZ, the first stage preamps P
1
have their reset switches turned on, i.e. are reset, so that their output is zero. Preamps P
2
are auto-zeroed during this phase of AZ. For the interpolating P
2
's, this also cancels any offset due to differences in the P
1
reset mode output voltages. During the second phase of AZ, the reset switches of preamps P
1
are turned off, and the preamps P
1
are auto-zeroed and their offsets are stored on the capacitors
18
.
The coupling capacitors
18
that connect the SH to the preamps P
1
thus store both the offset of P
1
and the reference voltages generated from resistor ladder
12
for P
1
. The consequence of this is that in order to auto-zero a P
2
′ preamp that interpolates between two P
1
preamps, both P
1
preamps must be reset during the first part of AZ. Since these P
1
s supply inputs not only for the P
2
being auto-zeroed, but also for their own P
2
s and the P
2
s both above and below them, a total of five outputs are affected by the auto-zero of one P
2
.
This means that, if one comparator is to be auto-zeroed at a time in the array and its output replaced with the output of an extra comparator, a problem exists. A total of five main array outputs are affected by the auto-zero: the comparator being auto-zeroed, the two above it, and the two below it. This is shown in
FIG. 2
, which shows the progression of AZ through the array. Question marks identify outputs being affected by the auto-zeroing process. The black preamps are the ones being auto-zeroed, and the gray ones are those that are not being auto-zeroed but which have outputs affected by the auto-zeroing process currently being performed.
SUMMARY OF THE INVENTION
The present invention involves a circuit architecture which combines two common flash ADC techniques used in high speed flash ADCs, described above, and which solves some of the problems that arise from combining these two techniques. In accordance with the present invention, a method is provided for performing an auto-zero function in a flash analog to digital converter (“ADC”), the ADC including a reference voltage circuit providing a plurality of evenly spaced analog reference voltages, and a plurality of system voltage comparators for comparing an input voltage against the reference voltages and providing an indication of which reference voltage corresponds to the input voltage. In the method the following steps are performed. A plurality of redundant voltage comparators is provided. A subset of the plurality of system voltage comparators is selected. Auto-zero is performed on the selected comparators, and the redundant comparators are used in the place of the selected comparators.
REFERENCES:
patent: 5194867 (1993-03-01), Fisher
patent: 5349354 (1994-09-01), Ito et al.
patent: 5459465 (1995-10-01), Kagey
patent: 6218975 (2001-04-01), Tsukamoto et al.
Sanroku Tsukamoto, et al., “A CMOS 6-b, 200 Msample/s, 3 V-Supply A/D Converter for a PRML Read Channel LSI,” IEEE Journal of Solid-State Circuits, vol. 31, No. 11, pp. 1831-1836, Nov. 1996.
Feygin Gennady
Martin David A.
Nagaraj Krishnasawamy
Brady III W. James
Jean-Pierre Peguy
Lauture Joseph J
Moore J. Dennis
Telecky , Jr. Frederick J.
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