Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage
Reexamination Certificate
2001-02-07
2003-04-01
Oda, Christine (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Frequency of cyclic current or voltage
C324S076380
Reexamination Certificate
active
06541952
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to electrical circuits, and more particularly to a system and method for reducing sampling mismatch in sample and hold circuits.
BACKGROUND OF THE INVENTION
Analog to digital converters (ADCS) are important analog circuit devices which take an analog input signal and generate one or more digital signals which are representative of the analog input. ADCs are used in many applications such as communications applications in which the components receive a voice input (an analog input) and transform the voice date into a digital format for internal processing. Exemplary applications using such ADCs are illustrated in prior art
FIGS. 1 and 2
, respectively. For example, in prior art
FIG. 1
, an exemplary base transceiver station (BTS)
10
is illustrated in which an RF analog input signal
12
is received, amplified and converted into a digital signal
14
before being processed in a baseband section
16
and network interface section
18
. Similarly, prior art
FIG. 2
illustrates a schematic diagram of an automobile multimedia system
20
in which various analog signals such as radio signals
22
and sensor signals
24
are transformed into digital signals for subsequent processing. Further, many other system applications exist, including, but not limited to, data communication receivers or hard disk drive (HDD) read channel applications such as the system
26
of prior art FIG.
3
.
One of the most challenging portions of an ADC is the sample and hold (S/H) circuit at the front end thereof. As the speed of ADCs continues to grow, the design of the S/H circuit becomes more challenging, and various solutions have been proposed to improve the speed of such S/H circuits. One prior art circuit solution for improving the speed of a S/H circuit is illustrated in prior art FIG.
4
and designated at reference numeral
30
. The S/H circuit
30
consists of four S/H subcircuits
32
a
-
32
d
coupled together in parallel. Each of the S/H subcircuits
32
a
-
32
d
operates individually as a S/H circuit, wherein the input V
IN
is passed to the output V
OUT
during a “sampling mode” and the state of the input is maintained on the output in the “hold mode”, respectively.
The speed of the S/H circuit
30
of
FIG. 4
is increased by using several individual S/H subcircuits
32
a
-
32
d
interleaved in time. An exemplary sample timing diagram for the S/H circuit
30
is illustrated in prior art FIG.
5
. Note that with multiple S/H subcircuits interleaved in time, each subcircuit transitions through one sample and hold cycle during four clock (CLK) cycles, whereas if a similar speed were desired with only a single S/H subcircuit, the sample and hold functions each would have to be completed within a one-half (½) clock cycle. Therefore in the above parallel interleaved configuration, the overall speed is increased without requiring higher performance from the individual S/H subcircuit elements.
Referring again to prior art
FIG. 4
, although the pass gates at the output of the overall S/H circuit
30
might seem like a possible speed limitation, usually such S/H circuits are followed by one or more output buffers. In such a case, the RC filter of the pass gate and the input capacitance of the output buffer is usually fairly small compared with the speed gained through parallelism.
One problem with the technique provided by the circuit
30
of prior art
FIG. 4
is that if the S/H subcircuits
32
a
-
32
d
are not perfectly matched, then errors can occur. The three chief types of mismatch associated with the interleaved S/H circuit
30
are offset mismatch, gain mismatch and sampling mismatch (which is sometimes referred to as timing mismatch). A brief discussion of the operation of an individual conventional S/H subcircuit is provided below in order to appreciate the impact that sampling mismatch has on the performance of the S/H circuits
30
.
An exemplary prior art sample and hold subcircuit is illustrated in prior art
FIG. 6
, and designated at reference numeral
40
. Circuit
40
is an exemplary detailed circuit of the structure
32
a
in FIG.
4
. Transistor M
1
operates as a sampling switch, and C
HOLD
acts as a sampling capacitor. In the sampling mode, a sampling signal “S” is asserted, thereby closing a switch
42
, which activates M
1
(turns M
1
on). With M
1
on, V
IN
is passed to the output V
OUT
.
A significant time point relating to sampling mismatch in S/H circuits deals with the instant when the sampling switch M
1
is deactivated, or turned off. Any deviation of the deactivation of M
1
from perfect CLK/N time periods will cause a sampling mismatch between the various subcircuits (e.g.,
32
a
-
32
d
) and result in distortion at the output V
OUT
(e.g., resulting in undesired “tones” at the output at f
in
±f
s
/N, wherein f
in
is the frequency of V
IN
, f
s
is the sampling frequency, and N represents the number of interleaved channels). To deactivate M
1
, the sample signal “S” goes low (opening switch
42
) and a hold signal “H” is asserted, which causes a switch
43
to close. This instance pulls the gate of M
1
down to ground, thus turning M
1
off. Each S/H subcircuit has its own hold signal “H”; consequently, a primary source of the sampling mismatch relates to mismatches in the switch M
1
driven by “H” and the arrival of the hold signal “H” at each subcircuit switch, respectively. In addition, even if no sampling mismatch occurs between the hold signals (“H”) of the various subcircuits
32
a
-
32
d,
a sizing mismatch of switch
43
or M
1
between the various subcircuits may exist which may contribute disadvantageously to sampling mismatch.
There is a need in the art for a circuit and method for increasing the speed in sample and hold circuits in which timing mismatch is reduced substantially.
SUMMARY OF THE INVENTION
According to the present invention, a system and method of reducing sampling mismatch in high speed S/H circuits is disclosed.
According to the present invention, sampling mismatch, for example, related to the sampling switch in various S/H subcircuits, is reduced by calibrating the subcircuits, for example, by modifying a delay associated with the hold signal of the subcircuits so as to minimize sampling mismatch between S/H subcircuits. In the above manner, the sampling mismatch between the various S/H subcircuits associated with the arrival of the hold signal at its switch in each subcircuit is reduced substantially or eliminated altogether.
The present invention is directed to a system and method for reducing sampling mismatch in high speed S/H circuits. In S/H circuits employing a plurality of time interleaved S/H subcircuits, sampling mismatch is reduced via calibration by modification of the hold signal to thereby establish a predetermined timing relationship between each of the S/H subcircuits. Such calibration is performed “on line”, thereby allowing for calibration of the S/H circuit without disconnecting the circuit chip from the signal path associated therewith in accordance with conventional “off line” calibration techniques.
According to one exemplary aspect of the present invention, calibration among a plurality of time-interleaved S/H subcircuits is accomplished by calibrating each S/H subcircuit separately with a pre-calibrated S/H subcircuit on-chip which serves as a calibration standard. Each calibration with the pre-calibrated S/H subcircuit provides an output result which is analyzed to identify sampling mismatch between the S/H subcircuit under test and the calibration standard. Such analysis is then used to modify the hold signal associated with the S/H subcircuit under test to minimize the timing mismatch.
Therefore the present invention provides for an “on line” calibration system and methodology as opposed to an “off line” type calibration. In order to fully appreciate several of the advantageous features of the present invention, a brief discussion follows below on how an “off line” calibration system operates. A detailed description of the “on line”
Brady W. James
Oda Christine
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Teresinski John
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