On-die thermal monitoring technique

Details On-die thermal monitoring technique On-die thermal monitoring technique

2003-01-23

2004-11-09

Meier, Stephen D. (Department: 2859)

Thermal measuring and testing

Temperature measurement

By electrical or magnetic heat sensor

C374S001000, C331S066000, C327S513000

Reexamination Certificate

active

06814485

ABSTRACT:

BACKGROUND OF INVENTION
A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system.
FIG. 1
shows a typical computer system (
10
) having a microprocessor (
12
), memory (
14
), integrated circuits (ICs) (
16
) that have various functionalities, and communication paths (
18
), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system (
10
).
Circuit elements in a microprocessor (
12
), and more generally, an IC (
16
), continue to get smaller. Accordingly, more and more circuit elements may be packed into an IC (
16
). In
FIG. 2
, a cross sectional diagram of a particular type of circuit element, a p-channel transistor (
200
), is shown. The p-channel transistor (
200
) includes two n+ regions (
204
,
206
) implanted in a p-substrate (
210
) or a p-well. The two n+ regions (
204
,
206
) form a drain and source region for the p-channel transistor (
200
). The depth of the drain and source regions may determine a junction (
209
) thickness for current to flow from one n+ region (
204
or
206
), through a channel formed below a gate (
202
) when the transistor (
200
) is “on,” to the other n+ region (
206
or
204
). A source contact (
212
) and drain contact (
214
) allow a connection with the n+ regions (
204
,
206
), respectively. The p-channel transistor (
200
) is separated from other devices by a field oxide (
230
,
232
).
The p-channel transistor (
200
) is controlled by a voltage potential on a gate (
202
). A gate contact (
216
) allows a connection with the gate (
202
). The gate (
202
) is separated from the p-substrate (
210
) by a gate oxide (
208
).
A voltage potential difference between the source contact (
212
) and drain contact (
214
) is denoted V
ds
. A voltage potential difference between the gate contact (
216
) and the source contact (
212
) is denoted V
gs
. The voltage potential to turn the p-channel transistor (
200
) “on,” i.e., allow the p-channel transistor (
200
) to conduct current, is a threshold voltage potential denoted V
t
.
FIG. 3
shows a diagram of a current-voltage characteristic for a typical metal-oxide transistor. As shown in
FIG. 3
, the p-channel transistor (
200
shown in
FIG. 2
) is “off” when |V
gs
|<|V
t
| (
255
). The p-channel transistor (
200
shown in
FIG. 2
) is “on” and in a linear region of operation when |V
ds
|≦|V
gs
−V
t
| and |V
gs
|≧|V
t
| (
265
). The p-channel transistor (
200
shown in
FIG. 2
) is “on” and in a saturation region of operation when |V
ds
|>|V
gs
−V
t
| and |V
gs
|≧|V
t
| (
275
).
As circuit elements in an IC (
16
shown in
FIG. 1
) continue to get smaller, features of the circuit elements, e.g., the gate oxide thickness, the depth of the two n+ regions (
204
,
206
shown in FIG.
2
), the spacing between the two n+ regions (
204
,
206
shown in FIG.
2
), etc., get smaller.
SUMMARY OF INVENTION
According to one aspect of the present invention, an apparatus comprising an integrated circuit where the integrated circuit comprises a thin gate oxide transistor; and a temperature monitoring system disposed on the integrated circuit comprising a first temperature independent voltage generator, a first temperature dependent voltage generator where the first temperature dependent voltage generator comprises a thick gate oxide transistor; and a first quantifier operatively connected to the first temperature independent voltage generator and the first temperature dependent voltage generator.
According to one aspect of the present invention, a method for monitoring temperature comprising generating a first temperature dependent voltage potential using at least one thick gate oxide transistor disposed on an integrated circuit having disposed thereon at least one thin gate oxide transistor; generating a first temperature independent voltage potential; and monitoring a temperature of the integrated circuit by operatively comparing the first temperature independent voltage potential and the first temperature dependent voltage potential.
According to one aspect of the present invention, an apparatus comprising means for computing a logic operation on an integrated circuit wherein the integrated circuit comprises a thin gate oxide transistor; means for generating a first temperature independent voltage potential; means for generating a first temperature dependent voltage potential using at least one thick gate oxide transistor; and means for operatively comparing the first temperature independent voltage potential and the first temperature dependent voltage potential to monitor a temperature of the integrated circuit.
According to one aspect of the present invention, an apparatus comprising an integrated circuit where the integrated circuit comprises a thin junction thickness transistor and a thick junction thickness transistor; and a temperature monitoring system disposed on the integrated circuit comprising a temperature independent voltage generator, a temperature dependent voltage generator, wherein the temperature dependent voltage generator comprises a thick junction thickness transistor; and a quantifier operatively connected to the temperature independent voltage generator and the temperature dependent voltage generator.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 4165642 (1979-08-01), Lipp
patent: 4443117 (1984-04-01), Muramoto et al.
patent: 4602871 (1986-07-01), Hanaoka
patent: 5100829 (1992-03-01), Fay et al.
patent: 5899570 (1999-05-01), Darmawaskita et al.
patent: 5966035 (1999-10-01), Lien
patent: 6476663 (2002-11-01), Gauthier et al.
patent: 2001/0021217 (2001-09-01), Gunther et al.
patent: 2003/0082842 (2003-05-01), Hwu et al.
patent: 2003/0155903 (2003-08-01), Gauthier et al.
patent: 2003/0155964 (2003-08-01), Gauthier et al.
patent: 2003/0156622 (2003-08-01), Gold et al.
patent: 2003/0158683 (2003-08-01), Gauthier et al.

Affiliated with

Also associated with

Rating

On-die thermal monitoring technique does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with On-die thermal monitoring technique, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-die thermal monitoring technique will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3289790