On-die termination method for multi-chip packages

Details On-die termination method for multi-chip packages On-die termination method for multi-chip packages

2006-06-14

2009-10-13

Nguyen, Cuong Q (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S691000, C257S737000

Reexamination Certificate

active

07602056

ABSTRACT:
An on-die termination method to support a multi-chip package routing topology is described. The on die termination method may increase the surface area on the substrate such that larger size die or more memory may be mounted thereto. The on-die termination method may include a semiconductor package that features on die termination bumps coupled to a semiconductor die's bus terminals, which couples the semiconductor die to an on-die termination pin coupled in the motherboard. An alternative on-die termination method includes a semiconductor die, within the multi-chip CPU package, designated as an end agent from which a single on die termination bump is coupled to an on-die termination pin.

REFERENCES:
patent: 5815427 (1998-09-01), Cloud et al.
patent: 2006/0151866 (2006-07-01), Lee
patent: 2007/0257340 (2007-11-01), Briggs et al.

Affiliated with

Also associated with

Rating

On-die termination method for multi-chip packages does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with On-die termination method for multi-chip packages, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-die termination method for multi-chip packages will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4142984