On-delay-compensating arm on-detection circuit

Details On-delay-compensating arm on-detection circuit On-delay-compensating arm on-detection circuit

2000-07-06

2001-09-11

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S588000

Reexamination Certificate

active

06288595

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an arm voltage pulse width detection circuit for an on
5
delay compensation circuit (also referred to as a “dead time compensation circuit”) for use in an inverter.
BACKGROUND
FIG. 4
shows an example of a conventional inverter circuit, wherein FIG.
4
(
a
) shows a main circuit section, and FIG.
4
(
b
) shows a control circuit section. In the inverter circuit in FIG.
4
(
a
), switching elements S
1
to S
6
constituting an upper arm and a lower arm alternately repeat an operation in which an upper switching element is turned on while a corresponding lower switching element is turned off, thereby controlling an output voltage. During this switching operation of the pair of switching elements, however, an operational delay in the control circuit or the switching elements may turn both switching elements on, causing a power source to be short-circuited. To prevent this, a period when both switching elements are simultaneously turned off is inserted into the switching period to preclude such a short circuit. This period is called “on delay.”
The insertion of on delay, however, may cause an error between the pulse width of the voltage to be output by the inverter and the pulse width of the voltage actually generated by the inverter, resulting in a decrease in output voltage or current distortion. Thus, methods are provided that compare a voltage command-value pulse width with the arm-voltage pulse width of the inverter to correct any error in the on/off ratio of the switching elements.
FIG.
5
(
a
) is a time chart showing an on-delay compensation operation in the case where a phase current flows from an inverter to a motor. FIG.
5
(
b
) is a time chart showing an on-delay compensation operation in the case where the phase current flows in the opposite direction, that is, from the motor to the inverter. In this case, a positive-potential side of a DC power source for an inverter main circuit is called a “P potential”, and a negative-potential side thereof is called an “N potential”. In FIG.
5
(
a
), since the arm voltage generated during an on-delay period (DT) is the N potential, a voltage error relative to a PWM pulse command occurs during the on-delay period of the upper arm. An on-delay compensator carries out compensation by comparing a PWM pulse-command input pulse width with an inverter-arm voltage pulse width to extend the on period of the upper arm by an amount corresponding to the resulting error in inverter-arm voltage pulse width as shown by the arrow.
In FIG.
5
(
b
), since the arm voltage generated during the on-delay period is the P potential, a voltage error relative to a PWM pulse command occurs during the on-delay period of the lower arm. An on-delay compensator carries out compensation as described above by comparing the PWM pulse-command input pulse width with the inverter-arm voltage pulse width to extend the on period of the lower arm by an amount corresponding to the resulting error in inverter-arm voltage pulse width as shown by the arrow.
The adoption of the above method requires the arm voltage pulse width of the inverter to be determined by a certain method. As shown in FIG.
4
(
a
), conventional methods generally divide the arm voltage Vuarm of the inverter, for example, by means of resistors R
10
, R
11
, compare the resulting values by means of comp
12
, and insulate the resulting output by means of a photo coupler PC
1
before input to the on delay compensator in FIG.
4
(
b
).
In the above pulse width detection circuit for inverter arm voltage based on the conventional method, however, voltage-dividing resistors having high resistance values are selected to reduce losses at the voltage-dividing resistance. Consequently, not only is the voltage prone to noise but the circuit also becomes equivalent to parallel connections of resistors and capacitors at high frequencies, thereby reducing detection accuracy. In addition, this circuit requires insulating elements such as photo couplers to insulate a control circuit from an inverter circuit, thereby inducing a detection delay.
Thus, when a circuit such as that in
FIG. 4
is used for the on-delay compensation, the accuracy of comparison between the PWM pulse-command input pulse width and the inverter-arm voltage pulse width decreases, preventing compensation of voltage errors. As a result, the accuracy of compensation for an error in inverter-arm voltage pulse width arising from the on delay decreases, causing non-uniform rotations in the case of motor control. In addition, a circuit such as that in
FIG. 4
requires a large number of external parts.
Therefore, the objects of the present invention are to reduce detection delay, to reduce the effects of noise, and to enable a detection circuit and a gate drive circuit to be integrated in order to reduce the number of external parts.
SUMMARY OF THE INVENTION
To attain these objects, according to the present invention, there is provided a detection circuit having arms each comprising a reverse parallel circuit including a semiconductor switching element and a free-wheel diode, the detection circuit detecting an on state of each of upper and lower arms of an inverter that converts a direct current into an alternating current, characterized in that: the semiconductor switching element on each of the upper and lower arms of the inverter is provided with a DC power source having its negative side connected to an emitter side of the semiconductor switching element, a first resistor connected to the positive side of the DC power source, a diode having an anode connected to the other terminal of the first resistor and a cathode connected to a collector of the semiconductor switching element, a reference potential having a negative side connected to the negative side of the DC power source, and a comparator to which the positive side of the reference potential and the potential of an anode-side terminal of the diode are input, in that each upper arm side is provided with a P channel FET having an output from the comparator connected to the gate thereof and the positive side of the DC power source connected to the source thereof to reduce the level of a comparator output signal, a second resistor connected between the drain of the FET and the emitter of the semiconductor switching element on the lower arm side, and a voltage detection section for detecting a terminal voltage of the second resistor, and in that an output from the voltage detection section and a comparator output from the lower arm side of the inverter are input to a compensation circuit as on-state detection signals for the upper and lower arms, respectively, with the compensation circuit operating to compensate for a voltage error between a command value and an actual value of a pulse width of an output voltage from the inverter, the error being caused by on delay.
Other advantages and features of the invention will become apparent from the following detailed description of the preferred embodiments of the invention and the accompanying drawings.


REFERENCES:
patent: 4597037 (1986-06-01), Okado
patent: 4772996 (1988-09-01), Hanei et al.
patent: 5818284 (1998-10-01), Murakami et al.

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