On-chip voltage generating device for semiconductor memory...

Details On-chip voltage generating device for semiconductor memory... On-chip voltage generating device for semiconductor memory...

1999-06-30

2001-01-09

Nelms, David (Department: 2818)

Static information storage and retrieval

Powering

Conservation of power

C365S222000, C365S226000, C365S233100

Reexamination Certificate

active

06172932

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an on-chip voltage generating device for semiconductor memory, and more particularly to an on-chip voltage generating device with reduced stand-by current during a self-refreshing mode period.
2. Description of the Prior Art
Generally, a semiconductor memory device includes a memory cell array of a two-dimensional matrix form with a rectangular type, a pheriperal circuit which enables the reading/writing operation from/to the memory cell array by the control of a plurality of external control signals and address signals, and data terminals through which data are input or output.
A dynamic memory device comprises a plurality of memory cells and an amount of charge stored on a capacitor of each memory cell is reduced due to a leakage with the lapse of time. For this reason, a refresh operation is periodically performed to recover the leakage charge amount on the capacitor.
As the refreshing operations, there are the RAS only refreshing mode with employment of the row-address strobe signal “RAS”, the CBR refreshing mode in which the column-address strobe signal “CAS” is set to a low level in advance before the row-address strobe signal “RAS” is set to a low level, and self-refreshing mode which determines by itself a refresh time and refresh addresses in response to a specific command and performs a refresh operation.
An object of the present invention is to provide a device which can reduce power consumption during a self-refresh period. The method or timing of the entry to the self-refresh mode is shown in FIG.
11
and
FIG. 12
in the timing diagram. As shown in the diagram, the self-refresh operation is performed by the control signals. Wherein
FIG. 11
indicates a self refresh operation in a Synchronous DRAM, and
FIG. 12
indicates a self refresh operation in a DRAM. The self-refresh signals shown in FIG.
11
and
FIG. 12
will be used in the on-chip voltage generating device of the present invention, and the function of them will be explained hereinafter.
In general, a DRAM comprises a memory cell array, a pheriperal circuit which controls row paths and column paths to access effective locations of the memory cell array, and an on-chip voltage generating circuit for supplying predetermined voltages to the memory cell array and the pheriperal circuit.
One of the important factors to reduce the current consumption is to control the operation of the on-chip voltage generating circuit. When the memory device enters a self refresh mode, only absolutely necessary external signals are enabled, but other signals remain in a turned-off state. Therefore, in this case, most of the current is consumed in the operation of the on-chip voltage generating devices, such as a low voltage generating device and a high voltage generating device.
Semiconductor memory generally includes a low voltage generating device which is used for the bulk bias voltage of the memory cell array and a high voltage generating device which is used for activating the word lines. The operation of these voltage generating devices may vary according to the operation mode of the memory device.
These voltage generating devices generally have two modes of operations.
One mode is a stand-by mode which indicates an inactive state when memory cell transistors and sense amplifiers are not activated.
Another mode is an active mode which indicates an active state when memory cell transistors and sense amplifiers are activated. This active state means that for example the data stored in the memory cell is delivered to the bit lines and the data are amplified by the sense amplifiers.
A large current is generally consumed when performing the active mode operation, thus more noise is caused in comparison to the operation in the stand-by mode. Accordingly, in consideration of this problem, power is generally sufficiently supplied to the conventional on-chip voltage generating device to perform a stable operation. This conventional on-chip voltage generating device operates in stand-by mode and active mode as shown in FIG.
1
.
In the diagram, the high voltage generating device comprises, a high voltage detector
1
and a high voltage generator
2
which operate in stand-by mode; and a high voltage detector
3
and a high voltage generator
4
which operate in active mode.
As illustrated above, the stand-by mode and the active mode are repeated during a self refresh operation.
The high voltage generating device, as shown in
FIG. 1
, comprises the high voltage generator
2
(i.e., small pumping circuit) for stand-by and the high voltage generator
4
(i.e., large pumping circuit) for active mode. Each of them has a corresponding voltage detector in order to determine the timing of a pumping operation by detecting the level of the high voltage.
The circuit construction of the high voltage detectors
1
and
2
shown in
FIG. 1
is indicated in detail in FIG.
2
and FIG.
3
.
In
FIG. 2
, the high voltage detector operating in stand-by mode comprises current mirror circuit and inverter means. During operation, in a case when a high voltage is decreased, the /PPEST is changed to a low level. Accordingly, the high voltage generator
2
shown in
FIG. 1
is operated.
Next, the operation of the high voltage detector for active mode with reference to
FIG. 3
will be illustrated. In the diagram, VPP indicates a high voltage higher than the power source voltage Vcc, and is the output voltage from the high voltage pumping device shown in
FIGS. 4 and 5
. The high voltage VPP is applied to the resistor R
1
and supplies current to the transistor MN
1
. The current amount in the transistor MN
2
may be similar to the current in the transistor MN
1
by the current mirror phenomenon. Therefore, when the voltage level of the high voltage VPP is increased, the current amount in the transistor MN
2
also proportionately increases. Accordingly, the voltage level of the node between the transistor MN
2
and the resistor R
2
is determined by the current amount which flows through the resistor R
2
. At this time, the voltage level of the signal “rasact” is maintained at a high level to enable the voltage detector. Accordingly, when the voltage VPP is increased, the current amount flowing through the transistors MN
1
and MN
2
also increases. Therefore, the signal /PPEAT is changed to a high level and is applied to the oscillator. As a result, the pumping operation may be stopped and the voltage VPP will no longer increase. If the voltage VPP is decreased, a reverse operation is conducted. Therefore, the pumping operation is activated to raise the voltage level of VPP.
As illustrated above, a current amount is used in the operation of the high voltage detector. In particular, the high voltage detector operating in stand-by mode always consumes a certain amount of current because it does not comprise a switching circuit which can control the turn on/off operation by itself. Therefore, the consumed current within the high voltage detector is considerable, so that power consumption eventually increase.
In particular, such a considerably consumed current causes negative effects in a self-refresh operation mode where a current consumption should be restricted.
In general, in an active mode during a self-refreshing operation, the effect of the amount of the operating current of the high voltage detector is not significant because the operating current of the sense amplifiers is considerable. However, in a stand-by mode during a self-refreshing operation, the effect of the amount of the operating current of the high voltage detector is significant on the power consumption of the memory device. Therefore, it is required to resolve such a problem by reducing or eliminating this unnecessary current consumption. Such a problem may also occur in a low voltage VBB generating device which generates a voltage VBB, such as a bulk bias voltage of the transistors which constitute cell transistors of the memory device. The function of the VBB is to control the threshold voltag

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