On chip test system for configurable gate arrays

Details On chip test system for configurable gate arrays On chip test system for configurable gate arrays

1985-06-26

1987-01-06

Fleming, Michael R.

Excavating

371 27, 371 67, 324 73R, G01R 3128

Patent

active

046352619

ABSTRACT:
An on chip test system for arrays is provided that includes self test and maintenance operation while allowing for both synchronous and pipeline modes of normal operation. The system is integrated on a chip that includes a plurality of inputs and a plurality of outputs. A plurality of gates are coupled between the plurality of inputs and outputs wherein input signals may be transmitted asynchronously to the gates and output signals may be transmitted asynchronously to the outputs. An input shift register is coupled between each of the inputs and the gates for synchronously transmitting input signals, and an output shift register is coupled between the gates and each of the outputs for synchronously transmitting output signals. A control logic circuit is coupled to the plurality of gates, the input shift registers, and the output shift registers for selecting the systems mode of operation. A comparator circuit is coupled to the output shift registers for comparing said output signals with expected signals.

REFERENCES:
patent: 4244048 (1981-01-01), Tsui
patent: 4357703 (1982-11-01), Van Brunt
patent: 4423509 (1983-12-01), Feissel
patent: 4471484 (1984-09-01), Sedmark
patent: 4517672 (1985-05-01), Pfleiderer
patent: 4519078 (1985-05-01), Komonytsky
patent: 4534028 (1985-08-01), Trischler
patent: 4584683 (1986-04-01), Shimizu
Resnick, D. R., "Testability and Maintainability with a New 6K Gate Array", VLSI Design, Mar./Apr. 1983.

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