On-chip substrate regulator test mode

Details On-chip substrate regulator test mode On-chip substrate regulator test mode

1995-08-30

1999-03-09

Karlsen, Ernest F.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324765, 327535, G01R 3126, H03K 3354

Patent

active

058805931

ABSTRACT:
An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating voltage level of the substrate. This is accomplished with a chain of MOSFETs that are configured to operate as a chain of resistive elements or diodes wherein each element in the chain may drop a portion of a supply voltage coupled to a first end the chain. The substrate is coupled to a second end of the chain. The substrate voltage level is essentially equivalent to the supply voltage level less the voltage drops across the elements in the diode chain. A charge pump maintains the substrate voltage level set by the chain. Performing chip testing with the substrate voltage level more negative than the normal negative voltage level facilitates detection of devices that will tend to fail only at cold temperatures. Performing chip testing with the substrate voltage level more positive than the normal negative voltage level facilitates detection of other margin failures and ion contamination.

REFERENCES:
patent: 4322675 (1982-03-01), Lee et al.
patent: 4553047 (1985-11-01), Dillinger et al.
patent: 4631421 (1986-12-01), Inoue et al.
patent: 4890011 (1989-12-01), Miyatake
patent: 5079744 (1992-01-01), Tobita et al.
patent: 5140554 (1992-08-01), Schreck et al.

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