On chip scrambling

Details On chip scrambling On chip scrambling

2002-06-28

2004-11-30

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S201000, C714S718000, C714S743000

Reexamination Certificate

active

06826111

ABSTRACT:

FIELD OF INVENTION
The invention relates to a method for the address-decoded operation of a semiconductor memory device in accordance with claim
1
and to a semiconductor memory device in accordance with claim
4
.
BACKGROUND
Semiconductor memory devices, for example DRAM memories, typically comprise at least one memory cell array in which a multiplicity of memory cells are arranged in a matrix-like manner. An individual memory cell is designed for storing binary data, i.e. a logic “0” or a logic “1”. These memory cells can be addressed in the matrix-like memory cell array by the specification of their assigned electrical address. The electrical address comprises, in a simplified fashion, a row specification and a column specification, i.e. an X value and a Y value.
However, modern semiconductor memory devices have complex memory cell arrays in which the so-called electrical address counting differs from the physical address counting. A physical address is in this case understood to be a physical position of a respective memory cell in the matrix-like memory cell array, which position is specified by X and Y coordinates. Consequently, if the intention is to address a specific memory cell with a physical address (X; Y), then the electrical address (X′; Y′) assigned to this memory cell must be known. Only if the physical addressing coincides with the electrical addressing can a memory cell with the physical position (X=5; Y=1), for example, be addressed by the inputting of the electrical address (X′=5; Y′=1). Generally, however, in order to address the memory cell with the specified physical address, it is necessary to input an electrical address that deviates therefrom, e.g. (X′=7; Y′=9).
This divergence of physical and electrical address counting causes considerable problems during the testing of the memory cell array which follows the fabrication of the semiconductor device. Thus, during the testing of the memory cell array, particular attention has to be directed toward a possibly functionally harmful interaction of adjacent memory cells. By way of example, the physical memory state of one memory cell (e.g. a positively or negatively charged storage capacitor) can influence an adjacent memory cell such that a write or read operation of this memory cell would lead to an incorrect result. In order to be able to preclude such possibly functionally harmful proximity effects of memory cells in the memory cell array, the cell array must be able to be brought into predetermined data topologies during the testing of the semiconductor device. A test of the memory cell array may, for example, involve testing whether error-free operation of the memory cell array is possible even when a chessboard topology of memory cells in a first and a second physical memory state (for example negatively and positively charged storage capacitors) is generated in the memory cell array.
In the same way, the order of access to the memory cells must also be taken into consideration during the testing of the memory cell array. In addition to the description of the test sequence of the semiconductor memory device, the so-called pattern encompassing the type of access, order of access and data topology, it is necessary, however, in modern semiconductor memory devices in which the physical and electrical address counting diverge, to program a so-called address scrambling in the test system used. This is because if the intention is to generate, for example, a chessboard topology in the memory cell array, then the test system must know the mapping or assignment of the electrical to the physical addresses of the memory cells. In order to bring a specific memory cell with a physical address (X; Y) into a specific physical memory state, the external test system must possess the assignment information in order to be able to output the electrical address required for addressing this memory cell to the semiconductor memory device.
On account of the continual advancing optimization of chip area and performance of modern semi-conductor memory devices, every new semiconductor memory device typically has a new, dedicated memory architecture, as a result of which there is a change in the items of assignment information between physical and electrical address counting. Consequently, every new semiconductor memory device requires a different address scrambling which must be programmed individually for this semiconductor memory device in the external test system. The programming of the external test systems is thus dependent on the respective semiconductor memory devices to be tested (the so-called DUT (device under test)). In many, in particular older, test systems, on account of the required data topologies whose complexity is constantly increasing, the program flexibility thereof no longer suffices for the required address scrambling. In any event, the programming of the test systems is very complicated and prone to errors.
Since external test systems are not subject to a uniform standard, moreover, each test system must be programmed individually. However, a semiconductor memory device typically passes through various test areas (for example bench, front-end test, back-end test and burn-in), various external test systems being used in each test area. An added difficulty is that a plurality of different test systems are possibly used within these test areas. By way of example, HP, Mosaid, IMS are used for the bench tests, Advantest and Teradyne are used for the front-end test and back-end test, and MTX and ANDO are used for the burn-in test. Individual address scrambling methods have to be programmed, if appropriate, for all these different test systems.
SUMMARY
In view of the disadvantages mentioned above, it is an object of the invention to specify a semiconductor memory device which can be tested in a simple manner by different external test systems. Furthermore, it is an object of the invention to specify a corresponding method.
According to the invention, a method for the address-decoded operation of a semiconductor memory device, in particular of a semiconductor memory device according to the invention, comprises the following steps:
provision of the semiconductor memory device having at least one memory cell array, which has a multiplicity of memory cells arranged in a matrix-like manner at least in regions, each of the memory cells being assigned a physical address (X; Y) corresponding to the physical position of the memory cell in the memory cell array and an electrical address (X′; Y′) corresponding to the electrical addressing of the memory cell in the memory cell array;
inputting of a physical address (X; Y) of a memory cell of the memory cell array that is to be addressed into an address input device of the semiconductor memory device;
decoding of the input physical address (X; Y) into the assigned electrical address (X′; Y′) of the memory cell to be addressed by an address decoder device of the semiconductor memory device; and
outputting of the electrical address (X′; Y′) to the memory cell array in order to address the memory cell to be addressed.
The method for address-decoded operation according to the invention accordingly relates to a semiconductor memory device having a memory cell array which is matrix-like at least in regions. Each memory cell of the memory cell array thus has a physical address corresponding to its physical position in the memory cell array. By way of example, the very top left memory cell has the physical address (X=0; Y=0). Each memory cell is also assigned an electrical address which—expressed in a simplified fashion—must be applied to the row and column decoders of the memory cell array in order to be able to effectively address said memory cell. If the physical and electrical address counting diverge in the semiconductor device, then the electrical address (X′; Y′) deviates, if appropriate, from the physical address (X; Y) of the memory

Affiliated with

Also associated with

Rating

On chip scrambling does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with On chip scrambling, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On chip scrambling will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3321611