On-chip pull-up circuit which may be selectively disabled

Details On-chip pull-up circuit which may be selectively disabled On-chip pull-up circuit which may be selectively disabled

1991-11-25

1993-08-17

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 3072961, H03K 19094

Patent

active

052372219

ABSTRACT:
An on-chip pull-up which can be selectively enabled/disabled comprises a pull-up transistor (e.g., an FET) connected between the line to be pulled up/down and a bias voltage (e.g., a positive voltage V.sub.DD or a negative voltage V.sub.SS). The control lead (e.g., gate lead) of the transistor is then made externally accessible. Connecting the control lead to V.sub.DD or V.sub.SS either enables or disables the pull-up depending on the particular transistor.

REFERENCES:
patent: 4223227 (1980-09-01), Taylor et al.
patent: 4481432 (1984-11-01), Davies, Jr.
patent: 4567575 (1986-01-01), Morihisia et al.
patent: 4833349 (1989-05-01), Liu et al.
patent: 4843262 (1989-06-01), Abe

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