Cryptography – Particular algorithmic function encoding – Nbs/des algorithm
Patent
1996-11-01
1998-11-24
Cangialosi, Salvatore
Cryptography
Particular algorithmic function encoding
Nbs/des algorithm
380 4, 326 39, H04L 900
Patent
active
058418679
ABSTRACT:
The present invention provides an efficient programming verification system for Programmable Logic Devices (PLDs). Based upon IEEE JTAG standard boundary scan test architecture, the invention provides a novel test architecture including a configuration register and a signature analyzer coupled between the TDI and TDO pins of the JTAG architecture. The configuration register of the invention comprises three parts: an address register/counter, a data register, a status register. The address register/counter performs dual functions depending upon an instruction received by an instruction register. The invention eliminates the need to load each address sequentially into the address register/counter for programming by enabling the address register/counter to auto-increment the address for memory locations. After loading an initial address value, the address register/counter automatically increments the address for programming memory cells. To verify PLD programming, the invention applies a signature analyzer coupled between the TDI and TDO pins. A single input linear feedback shift register (SISR) or multiple LFSR (MISR) can be used to implement a signature analyzer in accordance with the invention. SISR or MISR uses a characteristic polynomial to generate a near-unique signature checksum for an input sequence. The accumulated signature checksum is then provided serially through the TDO pin for inspection.
REFERENCES:
patent: 5315177 (1994-05-01), Zagar et al.
patent: 5485467 (1996-01-01), Golnabi
patent: 5541879 (1996-07-01), Suh et al.
patent: 5617021 (1997-04-01), Goetting et al.
patent: 5672966 (1997-09-01), Palczewski et al.
Curd Derek R.
Jacobson Neil G.
Cangialosi Salvatore
Harms Jeanette S.
Harriman J. D.
Xilinx , Inc.
LandOfFree
On-chip programming verification system for PLDs does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with On-chip programming verification system for PLDs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-chip programming verification system for PLDs will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1711938