On-chip programmability verification circuit for programmable re

Details On-chip programmability verification circuit for programmable re On-chip programmability verification circuit for programmable re

1986-04-03

1988-03-08

Hecker, Stuart N.

Static information storage and retrieval

Read only systems

Fusible

365201, G11C 1700, G11C 2900

Patent

active

047302739

ABSTRACT:
A Programmable Read Only Memory (PROM) and an on-chip programmability verification circuit is provided that allows for the verification of the programmability of lateral fuses. The PROM comprises a plurality of word lines, a plurality of bit lines, and a plurality of fuses, wherein each of the fuses are uniquely coupled between one of the word lines and one of the bit lines. A sense amplifier is coupled between each of the word lines and an output terminal. One each of a plurality of variable voltage current sources having a test voltage applied thereto is coupled to one of the sense amplifiers for providing a current to the sense amplifier, and in turn to the word line and fuse, wherein the resistance of the fuse in relation to a nominal value may be determined by comparing the test voltage and an output voltage on the output terminal.

REFERENCES:
patent: 4347584 (1982-08-01), Fukushima et al.
patent: 4625162 (1986-11-01), Bosnyak
patent: 4625311 (1986-11-01), Fitzpatrick et al.
patent: 4670708 (1987-06-01), Bosnyak et al.

Affiliated with

Also associated with

Rating

On-chip programmability verification circuit for programmable re does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with On-chip programmability verification circuit for programmable re, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-chip programmability verification circuit for programmable re will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-233919