Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
2002-06-26
2003-12-16
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
Reexamination Certificate
active
06664848
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to power systems for an integrated circuit and more particularly, to the reduction of noise on a bus of the power system supplying power to the integrated circuit.
BACKGROUND OF THE INVENTION
A load current supplied by a power source external to an integrated circuit varies with the workload of the integrated circuit. The variability in the load current supplied by the external power source to the integrated circuit results in a voltage noise component on an output signal of the power source. The integrated circuit includes a power grid that may include positive nodes, negative nodes, input nodes and output nodes. The noisy output signal is passed onto the power grid of the integrated circuit. The voltage noise component is due in part to the flow of the load current through inductances between the external power source and nodes of the power grid of the integrated circuit. As a result, a variable load current flows from a positive power grid node in the integrated circuit to a negative power grid node in the integrated circuit or from a negative power grid node of the integrated circuit to a positive power grid node of the integrated circuit and through an output signal node of the integrated circuit. Consequently, timing in the integrated circuit can be skewed and the reliability of the integrated circuit is possibly reduced due to voltage excursions on the power grid caused by the voltage noise component of the output signal from the external power source.
One conventional approach to reducing the variability of the load current is to increase an amount of on-chip charge storage capability either by adding decoupling capacitors or by increasing the size of the decoupling capacitors. A further step that is commonly taken in conjunction with increasing the amount of on-chip charge storage capability is to minimize integrated circuit packaging inductance and printed wiring board (PWB) inductance. One example of reducing the packaging inductance and the PWB inductance is the use of a ball grid array (BGA) package. Unfortunately this approach has a significant cost impact due to the additional on-chip decoupling capacitors and the specialized manufacturing processes and tools needed to manufacture PWB's and BGA packages.
Another known approach is to increase the passive series resistance value or reduce the passive parallel resistance value of the power bus of the integrated circuit. The thus changed passive resistance value further damps the resonant circuit formed by the stored charge of on-chip capacitance, the leads and the packaging of the integrated circuit, and the interconnections between the integrated circuit and the power source external to the integrated circuit. The term “damping” refers to a lowered “Q” or “quality factor” for the described resonant circuit. However, the change in the passive resistance results in a substantial increase in the amount of power dissipated by the integrated circuit and a loss of operating voltage magnitude.
Still another approach to reduce power bus noise voltage on a power bus of an integrated circuit caused by variability in a load current of the integrated circuit is AC damping. AC damping typically employs a circuit having a resistor in series with a capacitor for the purpose of reducing noise associated with a power source. The capacitance value of the capacitor must be a large fraction of the total on-chip capacitance of the integrated circuit, which, unfortunately, limits the availability of on-chip charge storage through a frequency response limiting resistance. Consequently, on-chip charge storage is not directly available from the on-chip storage capacitors at high noise frequencies values. The high noise frequency values are frequency values at or above the clock frequency of the integrated circuit. As a result, chip performance suffers due to an increase in switching time of the gates of the integrated circuit.
Another conventional approach to overcoming the problems associated with load current variability is the clamping of a power supply voltage to a nominal value plus a threshold value. This approach reduces the amount of voltage stress placed on the power bus or power grid of the integrated circuit in instances where the chip packaging and the PWB interconnect inductance have a relatively high value. This approach is less effective where the chip packaging and the PWB interconnection inductances have a modest inductance value. The reason for this is that the modest inductance value prevents the clamping of the power supply.
A further known approach generates a signal with a current value at about 180 degrees out of phase with the power supply noise voltage to null the noise component of the power signal. This approach is limited to about the resonant frequency of the on-chip power supply grid and has little effect in reducing power supply noise voltage at frequencies above the resonant frequency of the power grid. Unfortunately, power supply voltage noise often exceeds the resonant frequency of the power supply grid. Consequently, noise frequencies above the resonant frequency of the integrated circuit power grid go uncompensated.
Another approach to reducing a power supply noise voltage component creates an actively generated damping resistance with an upper frequency response limit that is determined by the device technology used to implement the actively generated damping resistance. Typically, the actively generated damping resistance devices are not responsive to power supply voltage noise frequencies at or above the clock frequency of the integrated circuit. As a consequence, the actively generated damping resistance provides no noise voltage reduction at or above the clock frequency of the integrated circuit.
SUMMARY OF THE INVENTION
The present invention addresses the above described limitations of reducing a noise voltage component from a power source external to, or off-chip from, an integrated circuit. In accordance with one aspect of the present invention, a noise voltage component from a power source coupled to an integrated circuit is offset between a first frequency cutoff value and a second frequency cutoff value to reduce a noise voltage amplitude on a power grid of the integrated circuit.
In one embodiment of the present invention, a circuit for reducing a noise component of a power signal on a power grid in an integrated circuit is provided. The circuit is configured as a damping circuit capable of providing a first current component at an output of the damping circuit when the noise component of the power signal is below a first cutoff frequency. The damping circuit is capable of providing a second current component at the output node of the damping circuit when the noise component of the power signal is at or above the first cutoff frequency. The second current component provided by the damping circuit flows in phase with the frequency of the noise component to reduce the noise component of the power signal on the power grid of the integrated circuit.
The ability to provide the second current component in phase with the noise component of the power signal, allows the circuit to provide a substantially linear resistance that is capable of damping the noise component without a substantial voltage drop commonly associated with parallel or series damping resistance. Consequently, the damping circuit lowers an effective impedance value for the power grid of the integrated circuit when a frequency value of the noise component reaches the first cutoff frequency. The damping circuit provides the effective impedance value at or above the first cutoff frequency up to a second cutoff frequency value limited by the inductance and capacitance associated with on-die electrical conductor physical layout.
In accordance with another embodiment of the present invention, a method is provided for offsetting a noise component of a power supply output signal received by an integrated circuit. The method includes the steps of producing a firs
Lahive & Cockfield LLP
Sun Microsystems Inc.
Zweizig Jeffrey
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