On-chip power supply boost for voltage droop reduction

Details On-chip power supply boost for voltage droop reduction On-chip power supply boost for voltage droop reduction

2001-03-27

2003-03-25

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S541000, C307S044000, C323S313000

Reexamination Certificate

active

06538497

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly, to integrated circuits having a stable power supply voltage.
BACKGROUND OF THE INVENTION
Advances in integrated circuit technology have resulted in higher density of devices, faster operating speeds, higher currents, and lower operating voltages. It is necessary to reduce noise on the power supply for correct operation at maximum speed.
One prior art method of maintaining a steady power supply voltage is to use one or more “decoupling” capacitors. These decoupling capacitors serve as charge buffers, sinking current during a positive voltage spike and supplying current during a negative voltage spike. For example, a fast increase in the current drawn by the integrated circuit may cause a drop in the power supply voltage, since the high rate of change in current is through the package inductance. This is referred to as a power supply voltage droop. To reduce the droop, a decoupling capacitor is used.
The size of the decoupling capacitor required increases with an increased rate of change of power supply current and increased package inductance for a given voltage droop. However, increasing the size of the decoupling capacitors can become expensive, if it increases the chip area or requires additional processing steps to integrate a large value capacitor onto an integrated circuit.
FIG. 1
shows a schematic layout of an integrated circuit using a prior art decoupling capacitor. An integrated circuit
101
includes multiple devices that draw a current
103
from a power supply
106
at a voltage V
dd
. When there is a fast increase in the current
103
drawn by the devices on the integrated circuit
101
, there will be a voltage droop in the power supply
106
. The high rate of current change is through a package inductance
107
, which in
FIG. 1
is shown to be coupled to a package resistance R
pkg
. To reduce the amount of the voltage droop, a significant part of the current can be supplied by an on-chip decoupling capacitor
109
, which is shown as being coupled to a resistance, R
die
.
However, as noted above, the formation of the on-chip decoupling capacitor may be expensive in terms of chip area and processing steps.


REFERENCES:
patent: 3886438 (1975-05-01), Bouman
patent: 4463270 (1984-07-01), Gordon
patent: 4528459 (1985-07-01), Wiegel
patent: 6000829 (1999-12-01), Kurokawa et al.
patent: 6040639 (2000-03-01), Ginell et al.
patent: 6097178 (2000-08-01), Owen et al.
patent: 6157178 (2000-12-01), Montanari

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