On-chip positive and negative high voltage wordline x-decoding f

Details On-chip positive and negative high voltage wordline x-decoding f On-chip positive and negative high voltage wordline x-decoding f

1996-02-05

1997-08-26

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 36518523, 36518911, 36523006, G11C 800

Patent

active

056616830

ABSTRACT:
An on-chip positive and negative high voltage wordline x-decoding system for EPROM/FLASH is disclosed wherein three transistors are required for each wordline. The x-decoding system minimizes system latch-up by separating the positive and negative high voltage portions of the system. The high-voltage portion of the x-decoding system includes a native mode PMOS transistor fabricated in a N-well on a common P-substrate and a high-voltage NAND gate that supplies a control signal to the gate of the PMOS transistor. In response to a variable power signal (which is at O VDC in erase mode, VCC in a read mode, and approximately +10 VDC in program mode) and the control signal (which is low when the memory cell is selected and the system is in read or program modes), the positive portion pulls the selected word line up to VCC and +10 VDC in read and program modes, respectively. The negative voltage portion of the system includes two NMOS transistors fabricated in a P-well within a separate N-well on the common P-substrate. Together, the NMOS transistors pull an unselected word line down to 0 VDC in program/write mode, to 0 VDC in read mode, and pull a selected word line down to -9 VDC in erase mode. In erase mode one of the NMOS transistors pulls an unselected word line down to 0 VDC. Latch-up is prevented by the double well configuration, which separates the positive and negative high-voltage decoding components.

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