On-chip PLL locked frequency determination method and system

Details On-chip PLL locked frequency determination method and system On-chip PLL locked frequency determination method and system

2005-05-10

2005-05-10

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By frequency

C327S044000

Reexamination Certificate

active

06891403

ABSTRACT:
The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.

REFERENCES:
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patent: 6384649 (2002-05-01), Boerstler et al.
patent: 6396889 (2002-05-01), Sunter et al.
patent: 6557117 (2003-04-01), Wu et al.
patent: 6661266 (2003-12-01), Variyam et al.

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