On-chip operation for memories

Details On-chip operation for memories On-chip operation for memories

1996-09-20

1998-02-17

Canney, Vincent P.

Excavating

371 211, 36523002, G06F 1100

Patent

active

057198802

ABSTRACT:
The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro-instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder with BILBO control (MID/BC), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and a subroutine stack (SS) to allow function calls. A program counter (PC) takes an index signal from the micro-instruction decoder with BILBO control (MID/BC) and a signal from the program counter multiplexer (PCM), and from those signal, generates a next microcode address. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip. Control instructions are easily modified to compensate for process and structure enhancements are made during the production lifetime of an integrated-circuit memory.

REFERENCES:
patent: 5329471 (1994-07-01), Swobodz et al.
patent: 5491660 (1996-02-01), Ashmore, Jr.

Affiliated with

Also associated with

Rating

On-chip operation for memories does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with On-chip operation for memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-chip operation for memories will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1789871