On-chip operation control for memories

Details On-chip operation control for memories On-chip operation control for memories

1994-11-18

1996-02-13

Nelms, David C.

Static information storage and retrieval

Addressing

Multiplexing

36518512, 365236, 36518902, 365239, 365240, G11C 700

Patent

active

054916607

ABSTRACT:
The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder (MID), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and an optional subroutine stack (SS) to allow function calls. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip. Control instructions are easily modified to compensate for process and structure enhancements are made during the production lifetime of an integrated-circuit memory.

REFERENCES:
patent: 4780855 (1988-10-01), Iida et al.
patent: 5327383 (1994-07-01), Merchant et al.
patent: 5347489 (1994-09-01), Merchant et al.
patent: 5359570 (1994-10-01), Hsu et al.

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