On chip network that maximizes interconnect utilization...

Multiplex communications – Pathfinding or routing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C370S396000

Reexamination Certificate

active

10207459

ABSTRACT:
A network that maximizes interconnect utilization between integrated processing elements, including ports, an interconnect, port interfaces, and an arbiter. Each port includes arbitration and data interfaces. The interconnect includes selectable data paths between the ports for packet datum transfer. Each port interface includes processing, source and destination interfaces. The source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. The destination interface receives packet datums via a number of available input buffers. Each transaction request includes a transaction size, a packet priority, and a destination port address. The arbiter includes a request queue and a buffer counter for each port and a datum counter for each acknowledged transaction. The arbiter arbitrates among transaction requests based on a selected arbitration scheme, destination buffer availability, data path availability, and priority, and uses the packet datum counters, arbitration latency and data path latency to minimize dead cycles in the interconnect.

REFERENCES:
patent: 4400771 (1983-08-01), Suzuki et al.
patent: 6108739 (2000-08-01), James et al.
patent: 6122680 (2000-09-01), Holm et al.
patent: 6317804 (2001-11-01), Levy et al.
patent: 6574688 (2003-06-01), Dale et al.
patent: 6715023 (2004-03-01), Abu-Lebdeh et al.
patent: 6725307 (2004-04-01), Alvarez et al.
patent: 6748479 (2004-06-01), Sano et al.
patent: 6751698 (2004-06-01), Deneroff et al.
patent: 2004/0215868 (2004-10-01), Solomon et al.
patent: 2004/0225781 (2004-11-01), Kotlowski et al.
Levy, Markus, “Motorola's MPC8540 Parts Ocean, Smart Peripherals and e500 Core Communicate Via Crossbar Switch,” Microprocessor Report, Dec. 17, 2001, pp. 1-4.
Guerrier, Pierre et al., “A Generic Architecture for On-Chip Packet-Switched Interconnections,” Universite Pierre et Marie Curie, 1999, pp. 1-7.
Bouvier, Dan, “RapidIO™, An Embedded System Component Network Architecture,”, Mar. 2000, pp. 1-19.
RapidIO Trade Association, RapidIO™ Interconnect Specification, Rev. 1.2, Jun. 2002, RapidIO Trade Association, pp. i-xxxvi and I-1-IV124.
Sonics Inc., Product Brief, “SiliconBackplane™ MicroNetwork,” 2002, 2 pages.
Sonic Inc., “SiliconBackplane MicroNetwork,” from http://www.sonicsinc.com/sonics/products/siliconbackplane, Copyright 2000-2002, Sonics Inc., 5 pages.
Sonics Inc., “Sonic μNetworks Technical Overview,” Jan. 2002, pp. i-viii and pp. 1-52.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

On chip network that maximizes interconnect utilization... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with On chip network that maximizes interconnect utilization..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On chip network that maximizes interconnect utilization... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3748215

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.