On-chip method of balancing memory detectors and balanced detect

Details On-chip method of balancing memory detectors and balanced detect On-chip method of balancing memory detectors and balanced detect

1979-06-13

1981-08-11

Moffitt, James W.

Static information storage and retrieval

Magnetic bubbles

Detectors

338195, G11C 1908

Patent

active

042837740

ABSTRACT:
A method of forming detector and dummy detector pair(s) of magnetoresistive elements on a bubble memory chip, with detector and dummy detector each having a balancing resistance network comprising parallel spaced apart end-connected lines of resistive material with the transverse legs (rungs) spaced between said parallel lines to form a ladder in-line (electrically) between the detector and pads for selectively balancing the pair(s), and for disconnecting certain rungs of the spaced apart end connected lines, if necessary, to change the path of current flow through the ladder and thus vary the resistance through the ladder. The product formed by the method comprises on-chip magnetoresistive detector element pair(s) including balancing resistance ladders, coupled in the current paths of the magnetoresistive elements, and having portions which can be selectively disconnected to change resistance of the ladder to balance the bridge network.

REFERENCES:
patent: 2261667 (1941-11-01), Stroszeck
patent: 3161858 (1964-12-01), Sanders et al.
patent: 3858189 (1974-12-01), Beausoleil et al.
patent: 3930304 (1976-01-01), Keller et al.
patent: 3952291 (1976-04-01), Bailey et al.
patent: 4035785 (1977-07-01), Kryder
patent: 4078230 (1978-03-01), George
patent: 4146867 (1979-03-01), Blangeard
patent: 4150366 (1979-04-01), Price
IBM Technical Disclosure Bulletin-vol. 13, No. 5, Oct. 1970, p. 1105.

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