Horology: time measuring systems or devices – Time interval – Electrical or electromechanical
Reexamination Certificate
2000-06-16
2001-12-04
Miska, Vit (Department: 2859)
Horology: time measuring systems or devices
Time interval
Electrical or electromechanical
C368S118000, C714S718000
Reexamination Certificate
active
06327224
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention generally relates to measuring timing characteristics of SRAM chips; and more specifically, the invention relates to timing measurements of data-pins spread and access times for such chips.
Traditionally, at-speed component test has guaranteed all AC timing specifications for SRAMs. The performance of high-speed SRAMs is presently limited, however, by tester accuracy in the measurement of input/output (I/O) timings. Specifically, access-time measurements, I/O pin-to-pin skew measurements, and echo-clock-to-data tracking measurements may only be externally determined to an accuracy of +/−200 ps or more. This external limitation can result in high-performance components becoming unnecessarily downgraded to lower performance applications. This downgrading results in a substantial reduction in high-performance applications and in a substantial reduction in high-performance product yield. In addition, the need for ever-increasing tester accuracy causes high test-equipment and manufacturing test costs.
For example, a device being tested for an access time of 1.5 ns will be subject to two external test constraints. First, the tester guardband is subtracted from the access-time strobe. For a typical high-speed tester, this guardband is 200 ps. Second, the access-time measurement is referenced to the worst-case (i.e., slowest) I/O of the chip. A 200 ps tester-induced pin-to-pin I/O spread results in an additional access time penalty because the access strobe must capture the slowest pin of the spread. In contrast to this wide spread induced by the tester, the pin-to-pin spread intrinsic to the SRAM can be as narrow as 30 ps for a well-matched design. A combined tester-imposed penalty of 300 ps from these two constraints requires that a device have an intrinsic access time of approximately 1.2 ns to meet a 1.5 ns specification at test. The same constraints apply for measurements of echo-clock to data tracking.
SUMMARY OF THE INVENTION
An object of this invention is to improve methods for measuring timing characteristics of SRAM chips.
Another object of this invention is to provide an on-chip method for measuring access time and data-pins spread of SRAMs.
These and other objectives are attained with a method and system for timing characteristics of an SRAM chip. The method comprises the steps of loading instructions onto the chip to activate sampling of data output, and detecting data output transitions. The method further comprises the steps of providing the chip with a test clock having a given state transition, and sweeping the test clock across detected data output transitions to identify timing characteristics of the circuit. Preferably this test clock is the JTAG clock.
The present invention may be used to measure either, or both, the data pins spread or access time of an SRAM. To do this, sweeping of the test pattern continues from the slowest data output transition detection to the fastest data output transition detection and proceeds until a given transition is detected on the SRAM clock. The difference in timing from the sampling of the slowest data output transition to the sampling of the fastest data output transition yields the data output pin-to-pin spread. The difference in timing from the,sampling of the slowest data output transition to the sampling of the transition of the SRAM clock yields the access time.
Guaranteeing critical AC timing specifications by design-assisted test, in accordance with the present invention, overcomes external tester measurement accuracy limitations. Design-assisted test is desirable because on-chip measurement circuitry provides an improvement in measurement accuracy over conventional external test methods. The preferred embodiments of the on-chip circuit techniques herein described measure SRAM access time with an accuracy of +/−30 ps and compare I/O-data to echo-clock timings with an accuracy of +/−10 ps.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.
REFERENCES:
patent: 4878209 (1989-10-01), Bassett et al.
patent: 5083299 (1992-01-01), Schwanke et al.
patent: 5181191 (1993-01-01), Farwell
patent: 5268639 (1993-12-01), Gassarro et al.
patent: 6243840 (2001-06-01), Raad et al.
patent: 2-184048 (1990-07-01), None
Abstract of Japanese Patent Application No. 09-171053, dated Jun. 30, 1997.
G.M. Belansek, et al., “Self-Timed Performance Test For Stand-Alone Random-Access Memories”, IBM Technical Disclosure Bulletin, vol. 30, No. 5, Oct. 1987.
O. Bula, et al., “Internal Access Time Measurements For Random-Access Memory Circuits”, IBM Technical Disclosure Bulletin, vol. 31, No. 7, Dec. 1988.
Braceras Geordie Maria
Pilo Harold
Pontius Dale E.
International Business Machines - Corporation
Miska Vit
Pepper Margaret A.
Scully Scott Murphy & Presser
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