On-chip loop filter for a PLL

Details On-chip loop filter for a PLL On-chip loop filter for a PLL

2006-08-08

2006-08-08

Vo, Nguyen T. (Department: 2685)

Telecommunications

Transmitter and receiver at same station

With frequency stabilization

C455S260000, C333S172000, C375S376000

Reexamination Certificate

active

07088962

ABSTRACT:
An on-chip loop filter includes a 1stresistor, a 1stcapacitor, a 2ndcapacitor, a 3rdcapacitor, a 2ndresistor, and a 4thcapacitor. The 1stresistor is operably coupled to receive a charge pump output. The 1stcapacitor is coupled in series with the 1stresistor where the second node of the 1stcapacitor is coupled to a return. The 2ndcapacitor is coupled in parallel with the series combination of the 1stresistor and 1stcapacitor. The 3rdcapacitor is coupled in parallel with the 2ndcapacitor. The 2ndresistor is coupled to a node of the 3rdcapacitor and to a node of the 4thcapacitor. The other node of the 4thcapacitor is coupled to ground. To enable these components to be placed on-chip, the 1stcapacitor is of a 1stcapacitor construct having a 1stquality factor, the 2ndcapacitor is of a 2ndcapacitor construct having a 2ndquality factor, where the 2ndquality factor is greater than the 1stquality factor, and the 3rdand 4thcapacitors are of a 3rdcapacitor construct having a 3rdquality factor, which is greater than the 2ndquality factor.

REFERENCES:
patent: 4736167 (1988-04-01), Kojima et al.
patent: 6115586 (2000-09-01), Bezzam et al.
patent: 6522223 (2003-02-01), Lobl et al.

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