On-chip interconnect-stack cooling using sacrificial...

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

Reexamination Certificate

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C361S679530, C361S699000, C361S718000, C257S713000, C257S714000, C438S122000

Reexamination Certificate

active

07936563

ABSTRACT:
The present invention relates to an integrated-circuit device and to a method for fabricating an integrated-circuit device with an integrated fluidic-cooling channel. The method comprises forming recesses in a dielectric layer sequence at desired lateral positions of electrical interconnect segments and at desired lateral positions of fluidic-cooling channel segments. A metal filling is deposited in the recesses of the dielectric layer sequence so as to form the electrical interconnect segments and to form a sacrificial filling in the fluidic-cooling channel segments. Afterwards, the sacrificial metal filling is selectively removed from the fluidic-cooling channel segments.

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English translation of JP 2005-294760 (published Oct. 20, 2005), machine translated on Mar. 7, 2011.
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