On-chip frequency degradation compensation

Details On-chip frequency degradation compensation On-chip frequency degradation compensation

2007-10-16

2007-10-16

Tang, Minh N. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010

Reexamination Certificate

active

10751132

ABSTRACT:
Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.

REFERENCES:
patent: 6535013 (2003-03-01), Saman
patent: 6724214 (2004-04-01), Manna et al.
patent: 6724268 (2004-04-01), Takahashi
patent: 6806698 (2004-10-01), Gauthier et al.
patent: 6903564 (2005-06-01), Suzuki
patent: 2005/0134394 (2005-06-01), Liu
patent: 2005/0140418 (2005-06-01), Muniandy et al.
Office Action mailed Apr. 18, 2006 in co-pending U.S. Appl. No. 10/745,427.
U.S. Appl. No. 11/096,777, filed Mar. 31, 2005, Liu et al.

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