On-chip fixed pattern noise canceling logarithmic response...

Details On-chip fixed pattern noise canceling logarithmic response... On-chip fixed pattern noise canceling logarithmic response...

2000-03-29

2002-03-12

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C348S302000

Reexamination Certificate

active

06355965

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to metal oxide semiconductor (MOS) image sensors and, more particularly, to logarithmic response image sensors.
BACKGROUND OF THE INVENTION
Integrated circuit technology has revolutionized various fields including computers, control systems, telecommunications, and imaging. In the field of imaging, the charge coupled device (CCD) sensor has made possible the manufacture of relatively low cost and small hand-held video cameras. Nevertheless, the solid-state CCD integrated circuits needed for imaging are relatively difficult to manufacture, and therefore are expensive.
An alternative low cost technology to CCD integrated circuits is the metal oxide semiconductor (MOS) integrated circuit. Not only are imaging devices using MOS technology less expensive to manufacture relative the CCD imaging devices, for certain applications MOS devices are superior in performance. For example, the pixel elements in a MOS device can be made smaller and therefore provide a higher resolution than CCD image sensors. In addition, the signal processing logic necessary can be integrated alongside the imaging circuitry, thus allowing for a single integrated chip to form a complete stand alone imaging device.
Two of the categories of CMOS image sensors are linear and logarithmic. In linear sensors, the exposure to light generates a small current in a photosensitive device (such as an inversely polarized photodiode), which is used to charge or discharge a capacitor during a fixed time interval. The voltage on the capacitor after the integration time is proportioned to the incident light intensity and the fixed integration time.
In logarithmic sensors, the current in the photosensitive device produced by the incident light is measured directly. The current is usually converted to voltage through a MOS transistor. This transformation follows a logarithmic function, and can have a very high dynamic range (on the order of 100-120 dB or higher).
FIG. 1
shows a basic prior art logarithmic sensing cell.
FIG. 1
has been reproduced from
FIG. 4
of “Design of a Foveated Log-Polar Image Sensor in Standard CMOS Technology” (F. Pardo et al.,
Design of Integrated Circuits and Systems
, DCIS '96, Sitges, Spain, November 1996). The following description is taken from that reference and explains how the cell works.
The current generated by the light in the photodiode flows through the transistor M
1
A. This current is very small (between pico and nano amperes), biasing the transistor in its weak inversion region. The second transistor M
2
A is just a source follower. In the weak inversion region, the simplified expression for the voltage between gate and source is:
V
gs
=
k
⁢
 
⁢
T
q
⁢
ln
⁢
 
⁢
(
L
W
⁢
I
d
I
do
)
(
1
)
where V
gs
is the gate-source voltage, I
d
is the drain current, W and L are the width and length of the transistor channel, T is the temperature, and k, q and I
do
are constants. From this expression, the logarithmic dependency of the voltage with the current can be seen. It directly means that the response (voltage) is logarithmic with the incident light intensity (current).
Other prior art circuits have attempted to improve the light sensitivity of the basic logarithmic sensing cell. U.S. Pat. No. 5,933,190, to Dierickx et al., shows several circuits designed for this purpose. In a first embodiment, the '190 patent proposes increasing the lengths of the gates of transistors such as the load transistor in a circuit similar to FIG.
1
. As a result of this increase in gate length, it is stated that the load transistor will saturate at lower current densities, and an increase in the sensitivity of the pixel for lower light intensities (current densities) will be achieved. This is based on the premise that the sensitivity of pixels at low light intensities may be limited by the leakage current through the load transistor.
Another embodiment in the '190 patent is shown in
FIG. 4
, which has been reproduced as
FIG. 2
herein. As illustrated in
FIG. 2
, the drain of the load transistor M
1
B is not directly tied to the output signal supply. The read-out means consists of a second MOSFET M
2
B which is not a source follower and finally, a third MOSFET M
3
B which acts as a switch. A current source I
B
provides a current with a magnitude in the order of microamperes. The gate of the transistor M
3
B is tied to the address.
While the photodiode D
B
can also be considered a current source (of the order of femtoamperes to nanoamperes according to the intensity of light impinging the photodiode) the transistor M
3
B is conducting the current decharging through the transistor M
2
B. Such current can be defined by:
I
2
~c(V
G
−V
th
)  (2)
wherein c is a constant value.
As I
2
is given by the current source and is more or less a constant, we have then V
G
also nearly a constant. Therefore, the light acquired by the photodiode D
B
is converted into a voltage drop across the load transistor M
1
B. Accordingly, this pixel has similar functions as the one described in FIG.
1
. Alternatively, this pixel can also be considered as a simple and classic resistive feedback amplifier.
As discussed in “On-Chip Offset Calibrated Logarithmic Response Image Sensor” (S. Kavadias et al., 1999
IEEE Workshop on Charge
-
Coupled Devices and Advanced Image Sensors
, pp. 68-71), the major drawback of logarithmic CMOS image sensors (such as those illustrated in
FIGS. 1 and 2
) compared with their linear counterparts is the increased Fixed Pattern Noise (FPN). This noise is caused from the non-uniformities of the parameters associated with the various devices present on the sensor chip. It appears as an offset in the output signal delivered by each pixel. In linear integrating sensors the photocurrent is integrated on a capacitance over a well-defined time period, therefore methods for the elimination of this offset have been proposed based on the readout of the voltage of the integrating capacitance during two states. One widely used technique in linear integrating sensors is “correlated double sampling”.
Sensors employing pixels with logarithmic response are very attractive devices in applications where a high dynamic range is required. However, they suffer from high FPN due to the non-availability of two distinct pixel levels as in the case of linear integrating sensors. A few prior art circuits have attempted to address the problem of the high FPN in logarithmic image sensors. One general approach has been to develop a known reference for each pixel, against which the output of the signal can be calibrated.
One way to develop a known reference level for each pixel circuit in an array is to use a known reference current to produce an output from the pixel circuit, similar to how the current from a photodiode would produce an output. By using a known reference current for each of the pixel circuits, a reference level for each of the pixel circuits can be obtained. This technique is described in more detail in “On-Chip Offset Calibrated Logarithmic Response Image Sensor” (supra).
FIGS. 1 and 2
of that reference have been reproduced as
FIGS. 3A and 3B
herein.
FIG. 3A
shows a basic pixel structure, where transistor M
1
C acts as the bias of the photodiode and provides the logarithmic response. Transistor M
2
C is the driver transistor of the on-pixel source follower and transistor M
3
C is used for row selection. Transistor M
4
C connects the pixel to the calibration source I
CAL
which is common for pixels lying on the same column. Transistor M
5
C connects the output of photodiode D
C
to the gate of transistor M
2
C. The calibration process is accomplished in two states. First, transistor M
4
C is switched off and the pixel voltage is stored. This voltage is logarithmically related to the photocurrent delivered by the photodiode D
C
. Then transistor M
4
C is switched on and the pixel output is again sampled and extracted from the previous level. The difference between these two levels has a very small off

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