On-chip fixed-pattern noise calibration for CMOS image sensors

Details On-chip fixed-pattern noise calibration for CMOS image sensors On-chip fixed-pattern noise calibration for CMOS image sensors

1998-11-04

2003-03-25

Garber, Wendy R. (Department: 2612)

Television

Camera, system and detail

Combined image signal generator and general image signal...

C348S308000, C250S208100

Reexamination Certificate

active

06538695

ABSTRACT:

FIELD OF INVENTION
The present invention relates to complementary metal oxide semiconductor image sensors, and more particularly, to methods for on-chip calibration and correction of fixed-pattern noise.
BACKGROUND OF INVENTION
Complementary metal oxide semiconductor (CMOS) image sensor technology is poised to take over the existing CCD (charge-coupled-device) technology in the market of image and video capture. CMOS technology offers many benefits, such as lower cost, ease of manufacturing, and a higher degree of integration over the CCD. However, a major drawback of the CMOS image sensor technology is the presence of fixed-pattern noise (FPN). This type of noise is generated from a mismatch of circuit structures in the integrated circuits process variations. The effect of FPN is that groups of pixels, typically each column in a sensor array exhibits relatively different strengths in their responses to uniform input light.
To remove the effect of FPN, conventional calibration process involves measuring an output based on a known optical input and comparing it against an expected value. In CMOS image sensors, a white light of known intensity is typically shone onto the sensors and used as the input calibration signal. In principle, if there is no mismatch in the sensor devices, the voltage signal output from every pixel cell should be identical. In reality, significant differences in signal output values are read out between bit lines for the pixel columns of a sensor matrix, even if the same input light stimulus is applied to the matrix. These column differences can be calibrated and stored to be used in the normal FPN correction process. Typically, these difference data are stored separately in a separate, off-chip, non-volatile memory device, and during FPN correction process, the deviation data is then used to compensate each bit line output to produce a corrected pixel output value. However, an external non-volatile memory unit increases cost and provides lower performance to access this off-chip device. Moreover, a non-volatile memory is an expensive component to be integrated on-chip as well. There is therefore a need for a high performance, cost-effective CMOS sensors with minimum FPN.
SUMMARY OF INVENTION
An on-chip FPN calibration method and circuits scheme applies a reference voltage signal to an array of calibration pixels coupled to a sensor matrix. Two data values are read from each bit line and used to calculate an offset and a gain error for a pixel column, the offset being the first data value and the gain error being the slope of the first and second data value read for each bit line. A reference offset and a reference gain error value are then generated by computing the average offset and the average gain error from the collected offset and gain error values of each bit line. Calibration data for each bit line then comprises an offset difference and a gain error difference, the offset difference comprising the difference between the offset value for that bit line and the reference offset, and the gain error difference comprising the gain error difference between the gain error for that bit line and the reference gain error. The calibration data for each bit line is then stored in on-chip volatile memory and is used later under normal operation to compensate for the FPN effect.


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