Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-07-27
2003-12-09
Sterrett, Jeffrey (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S281000
Reexamination Certificate
active
06661213
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is related to integrated circuits and integrated circuit technology, and in particular, to integrated circuit low noise/analog power supplies.
2. Background Information
One limitation of the circuit
100
is poor frequency performance by the LC filter
106
, and as a result, for the circuit
100
overall. This is because the inductor
108
has parasitic capacitance and the capacitor
110
has parasitic inductance.
FIG. 2
is a graphical representation a response curve
200
for the LC filter
106
, which shows a pole
201
at fifteen kilohertz (kHz), where the gain of the circuit
100
is reduced by approximately 3 dB. This means that at fifteen kHz the gain of the circuit
100
is half of what the gain is at zero hertz.
FIG. 1
shows a block diagram of a typical circuit
100
used to filter a microprocessor core voltage supply
102
and generate an analog voltage supply
104
. The circuit
100
includes an inductor-capacitor (LC) filter
106
, which is a low pass filter. This means that the LC filter
106
when operating as desired, allows low frequencies to pass through it and attenuates high frequencies. The LC filter
106
includes an inductor
108
and a capacitor
110
. The analog voltage supply
104
is coupled to a phase locked loop (PLL) circuit
112
. The PLL circuit
112
is located on a microprocessor
120
. The return path for the analog voltage supply
104
is a return path
114
.
One limitation of the circuit
100
is poor frequency performance by the LC filter
106
, and as a result, for the circuit
100
overall. This is because the inductor
108
has parasitic capacitance and the capacitor
110
has parasitic inductance.
FIG. 2
is a graphical representation a response curve
200
for the LC filter
106
, which shows a pole at fifteen kilohertz (kHz), where the gain of the circuit
100
is reduced by approximately 3 dB. This means that at fifteen kHz the gain of the circuit
100
is half of what the gain is at zero hertz.
Also shown in
FIG. 2
is a notch
202
at one megahertz (MHz). At frequencies higher than one MHz, the gain of the circuit
100
increases significantly, which is the opposite of the desired frequency performance.
The response curve
200
also shows a reflection portion
204
. The reflection portion
204
indicates that at frequencies higher than or equal to one MHz the LC filter
106
begins to pass high frequencies, which is undesirable.
FIG. 2
also shows another limitation of the circuit
100
, which is the noise amplification at Fpeak
206
(or peak frequency) due to the second order nature of the LC filter
106
. The noise amplification may degrade the phase noise performance of the PLL circuit
112
.
A further limitation of the circuit
100
is that when the core voltage supply
102
changes the analog voltage supply
104
to the PLL circuit
112
changes accordingly. For example, operation in wide ranges of variations in the analog voltage supply
104
may degrade the PLL circuit
112
's performance. Wide ranges in the analog voltage supply
104
also may cause the PLL circuit
112
to cease operating.
Another limitation is that each phase locked loop circuit has its own inductor-capacitor filter. This means that as the number of phase locked loop circuits increases the number of LC filters, and individual capacitors and inductors, increases.
Moreover, the prior art LC filter
106
is typically located on a computer's motherboard. This can mean a large number of components on each motherboard, depending on the number of PLL circuits
112
in a particular processor.
REFERENCES:
patent: 4525663 (1985-06-01), Henry
patent: 5334928 (1994-08-01), Dobkin et al.
patent: 5625278 (1997-04-01), Thiel et al.
patent: 5787014 (1998-07-01), Hall et al.
patent: 5847552 (1998-12-01), Brown
patent: 6046577 (2000-04-01), Rincon-Mora et al.
patent: 6114843 (2000-09-01), Olah
patent: 6175224 (2001-01-01), Kadanka
patent: 6313615 (2001-11-01), Fayneh et al.
patent: 6446212 (2002-09-01), Smit et al.
Fayneh Eyal
Knoll Ernest
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Sterrett Jeffrey
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