On-chip ESD protection circuit for compound semiconductor...

Details On-chip ESD protection circuit for compound semiconductor... On-chip ESD protection circuit for compound semiconductor...

2007-05-30

2008-08-05

Jackson, Stephen W (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S111000, C361S018000

Reexamination Certificate

active

07408752

ABSTRACT:
A low loading capacitance on-chip electrostatic discharge (ESD) protection circuit for compound semiconductor power amplifiers is disclosed, which does not degrade the circuit RF performance. Its principle of operation and simulation results regarding capacitance loading, leakage current, degradation to RF performance are disclosed. The design, loading effect over frequency, robustness over process and temperature variation and application to an RF power amplifier is presented in detail. The ESD circuit couples an input to ground during ESD surges through a diode string coupled to the input, and a transistor switch or Darlington pair having its gate coupled to and triggered by the diode string. The Darlington pair couples the input to ground when triggered through a low impedance path in parallel to the diode string. A reverse diode also couples ground to the input on reverse surges.

REFERENCES:
patent: 5774318 (1998-06-01), McClure et al.
patent: 6529059 (2003-03-01), Davis
patent: 7280332 (2007-10-01), Ma et al.
patent: 2002/0130392 (2002-09-01), Brennan et al.

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