On-chip differential resistance technique with noise immunity an

Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Parallel controlled paths

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

327308, H03K 1762, H03L 500

Patent

active

059559110

ABSTRACT:
An on-chip resistance to an input current of an input signal includes a parallel transistor resistor and a control circuit for biasing the transistors of the parallel transistor resistor. The parallel transistor resistor includes first and second transistors of first and second types. Each transistor includes first and second current handling terminals and a control terminal. The control terminals are coupled to receive control signals from the control circuit. The first current handling terminals are coupled to provide an input node for receiving an input signal, and the second current handling terminals are coupled to provide an output signal. The control circuit is coupled to provide the first and second control signals for biasing the respective first and second transistors so that a first derivative of a resistance of the parallel transistor resistor in relation to an input-to-output voltage is zero at a selectable operation point.

REFERENCES:
patent: 4611135 (1986-09-01), Nakayama et al.
patent: 5359235 (1994-10-01), Coyle et al.
patent: 5378950 (1995-01-01), Takamoto et al.
patent: 5430408 (1995-07-01), Ovens et al.
patent: 5477169 (1995-12-01), Shen et al.
patent: 5634014 (1997-05-01), Gist et al.
patent: 5831453 (1998-11-01), Stamoulis et al.
Kyeongho Lee, Sungjoon Kim, gijung Ahn, and Deog-Kyoon Jeong; "A CMOS Serial Link for Fully Duplexed Data Communication," IEEE Journal of Solid-State Circuits, vol. 30, No. 4, Apr. 1995, pp. 353-364.
Randy Mooney, Charles Dike, and Shekhar Borkar; "A 900 Mb/s Bidirectional Signaling Scheme," IEEE Journal of Solid-State Circuits, vol. 30, No. 12, Dec. 1995, pp. 1538-1543.
Jan M. Rabaey, Digital Integrated Circuits, "Designing Combinational Logic Gates in CMOS," Prentice Hall, 1996, pp. 213-214.
Paul Horowitz and Winfield Hill, The Art of Electronics Second Edition, Cambridge University Press, New York, NY, 1980, 1989, pp. 142-143.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

On-chip differential resistance technique with noise immunity an does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with On-chip differential resistance technique with noise immunity an, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-chip differential resistance technique with noise immunity an will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-83787

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.